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DS3134 数据表(PDF) 95 Page - Dallas Semiconductor

部件名 DS3134
功能描述  Chateau Channelized T1 And E1 And HDLC Controller
PDF  203 Pages
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制造商  DALLAS [Dallas Semiconductor]
网页  https://www.maximintegrated.com/en.html
标志 DALLAS - Dallas Semiconductor

DS3134 数据表(HTML) 95 Page - Dallas Semiconductor

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DS3134
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Register Name:
TFLWM
Register Description: Transmit FIFO Low Water Mark
Register Address:
09A4h
76
5432
10
TLWM7
TLWM6
TLWM5
TLWM4
TLWM3
TLWM2
TLWM1
TLWM0
15
14
13
12
11
10
9
8
n/a
n/a
n/a
n/a
n/a
n/a
TLWM9
TLWM8
Note: Bits that are underlined are read only, all other bits are read-write.
Bits 0 to 9 / Low Water Mark (TLWM0 to TLWM9). These 10 bits indicate the setting of the
Transmit Low Water Mark. The Low Water Mark setting is the number of Blocks left in the Transmit
FIFO before the DMA will get more data from the PCI Bus. The Low Water Mark setting must be
between (inclusive) 1 block and one less than the number of blocks in the link list chain for the particular
channel involved. For example, if five blocks are linked together, then the Low Water Mark can be set to
1, 2, or 3. In another words the Low Water Mark can be set at a value of 1 to N – 2, where N = number of
blocks are linked together. Any other numbers are illegal.
0000000000 (000h) = invalid setting
0000000001 (001h) = Low Water Mark is 1 Block
0000000010 (002h) = Low Water Mark is 2 Blocks
0111111111 (1FFh) = Low Water Mark is 511 Blocks
1111111111 (3FFh) = Low Water Mark is 1023 Blocks



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