DS3134 datasheet(5/203 Pages) DALLAS

5 / 203 page

DS3134

5 of 203

TABLE OF CONTENTS

Section 1: Introduction……………………………………………………………………………………..7

Section 2: Signal Description…………………………………………………………………………… 16

2.1 Overview / Signal Lead List………………………………………………………………… 16

2.2 Serial Port Interface Signal Description……………………………………………………

2.3 Local Bus Signal Description………………………………………………………………. 24

2.4 JTAG Signal Description…………………………………………………………………… 27

2.5 PCI Bus Signal Description………………………………………………………………… 28

2.6 Supply & Test Signal Description…………………...…………………………………….. 31

Section 3: Memory Map………………………………………………………………………………… 32

3.0 Introduction………………………………………………………………………………….. 32

3.1 General Configuration Registers…………………………………………………………..

3.2 Receive Port Registers……………………………………………………………………..

3.3 Transmit Port Registers……………………………………………………………………. 33

3.4 Channelized Port Registers………………………………………………………………..

3.5 HDLC Registers……………………………………………………………………………. 35

3.6 BERT Registers…………………………………………………………………………….. 35

3.7 Receive DMA Registers……………………………………………………………………. 35

3.8 Transmit DMA Registers…………………………………………………………………… 36

3.9 FIFO Registers……………………………………………………………………………… 36

3.10 PCI Configuration Registers for Function 0…………………………………………….

3.11 PCI Configuration Registers for Function 1…………………………………………….

Section 4: General Device Configuration & Status/Interrupt………………………………………….. 37

4.1 Master Reset & ID Register Description………………………………………………….

4.2 Master Configuration Register Description……………………………………………….

4.3 Status & Interrupt…………………………………………………………………………… 40

4.3.1 Status & Interrupt General Description………………………………………

4.3.2 Status & Interrupt Register Description………………………………………

4.4 Test Register Description…………………………………………………………………..

Section 5: Layer One…………………………………………………………………………………… 51

5.1 General Description………………………………………………………………………… 51

5.2 Port Register Description…………………………………………………………………..

5.3 Layer One Configuration Register Description…………………………………………..

5.4 Receive V.54 Detector……………………………………………………………………..

5.5 BERT…………………………………………………………………………………………69

5.6 BERT Register Description………………………………………………………………..

Section 6: HDLC………………………………………………………………………………………… 77

6.1 General Description………………………………………………………………………..

6.2 HDLC Register Description……………………………………………………………….

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