Bits 7–0

This register determines the output of DAC 2. The full-scale output is determined by bit 5 of the DAC

Config, OSD Contrast & DC Offset Register.

DAC 3 Register

Register Name (address): DAC3CTRL (0x8436)

7

654321

0

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

Bits 7–0

This register determines the output of DAC 3. The full-scale output is determined by bit 5 of the DAC

Config, OSD Contrast & DC Offset Register.

DAC 4 Register

Register Name (address): DAC4CTRL (0x8437)

7

654321

0

BA7

BA6

BA5

BA4

BA3

BA2

BA1

BA0

Bits 7–0

This register determines the output of DAC 4. The output of this DAC can be scaled and mixed with the

outputs of DACs 1–3 as determined by bit 6 of the DAC Config, OSD Contrast & DC Offset Register.

DAC Config, OSD Contrast & DC Offset Register

Register Name (address): DACOSDDCOFF (0x8438)

7

654321

0

RSV

DCF1

DCF0

OSD1

OSD0

DC2

DC1

DC0

Bits 2–0

These determine the DC offset of the three video outputs, blue, red and green.

Bits 4–3

These determine the contrast of the internally generated OSD.

Bit 5

When this bit is a 0, the full-scale outputs of DACs 1–3 are 4.5V. When it is a 1 the full-scale level is

2.5V.

Bit 6

When this bit is a 0, the DAC 4 output is independent. When it is a 1, the DAC 4 output is scaled by

50% and added to the outputs of DACs 1–3.

Bit 7

Reserved and should be set to zero.

Global Video Control Register

Register Name (address): GLOBALCTRL (0x8439)

7

654321

0

RSV

RSV

RSV

RSV

RSV

RSV

PS

BV

Bit 0

When this bit is a 1, the video outputs are blanked (set to black level). When it is a 0, video is not

blanked.

Bit 1

When this bit is a 1, the analog sections of the preamplifier are shut down for low power consumption.

When it is a 0, the analog sections are enabled.

PLL Range Register

Register Name (address): PLLFREQRNG (0x843E)

7

654321

0

RSV

RSV

CLMP

RSV

OOR

VBL

PFR1

PFR0

Bits 1–0

These determine the optimum frequency range of the Phase Locked Loop. Please see Table 3 for

recommended register values for various horizontal scan rates.

Bit 2

This is the Vertical Blanking register. When this bit is a 1, vertical blanking is gated to the video outputs.

When set to a 0, the video outputs do not have vertical blanking.

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