Figure 4 and Figure 5 show the case where the horizontal and vertical inputs are from deflection. Figure 4 shows the pin 24

voltage which is derived from a horizontal flyback pulse of 35 volts peak to peak with R

shows the pin 1 voltage which is derived from a vertical flyback pulse of 55 volts peak to peak with C

Figure 6 shows the pin 23 clamp input voltage superimposed on the neck board clamp logic input pulse. R

chosen to limit the pin 23 voltage to about 2.5V peak to peak. This corresponds to the application circuit given in Figure 9.

Cathode Response

Figure 7 shows the response at the red cathode for the application circuit in Figures 9, 10. The input video risetime is 1.5

nanoseconds. The resulting leading edge has a 7.1 nanosecond risetime and a 7.6% overshoot, while the trailing edge has a 7.1

nanosecond risetime and a 6.9% overshoot with an LM2467 driver.

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FIGURE 4. Deflection Horizonal Blanking

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FIGURE 5. Deflection Vertical Blanking

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FIGURE 6. Logic Clamp Pulse

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FIGURE 7. Red Cathode Response

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