AS4C32M16D2 datasheet(21/70 Pages) ALSC

21 / 70 page

AS4C32M16D2

Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070

TEL: (650) 610-6800

FAX: (650) 620-9211

Alliance Memory Inc. reserves the right to change products or specification without notice.

Rev. 1.1

Feb. /2013

 Auto precharge operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge

Command or the auto-precharge function. When a Read or a Write Command is given to the DDR2 SDRAM, the CAS#

timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at

the earliest possible moment during the burst read or write cycle. If A10 is LOW when the READ or WRITE Command

is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of

the burst sequence. If A10 is HIGH when the Read or Write Command is issued, then the auto-precharge function is

engaged. During auto-precharge, a Read Command will execute as normal with the exception that the active bank

will begin to precharge on the rising edge which is CAS latency (CL) clock cycles before the end of the read burst.

Auto-precharge also be implemented during Write commands. The precharge operation engaged by the Auto

precharge command will not begin until the last data of the burst write sequence is properly stored in the memory

array. This feature allows the precharge operation to be partially or completely hidden during burst Read cycles

(dependent upon CAS latency) thus improving system performance for random data access. The RAS# lockout circuit

internally delays the Precharge operation until the array restore operation has been completed (tRAS satisfied) so that

the auto precharge command may be issued with any Read or Write command.

AS4C32M16D2 数据表(PDF) 21 Page - Alliance Semiconductor Corporation