STV7620M

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CIRCUIT DESCRIPTION

STV7620M includes all the logic and power cir-

cuits necessary to drive column electrodes of a

Plasma Display Panel (P. D. P.). Binary values of

each pixel of the displayed line are loaded into the

shift register by a 6 bit wide (A1 - A6) or 3 bit wide

(A1 - A3) data bus, depending on the configuration

of the BS input pin. Data is shifted at each low-to-

high transition of the CLK clock.

The forward/reverse (F/R) input is used to select

the direction of the shift register.

The BS input sets the configuration of the shift reg-

ister either in 3 x 32 bits or in 6 x 16 bits.

In case of a 3 bit arrangement, A1, A2 and A3 data

bus input pins are used. The 3 shift registers are

loaded with 32 clock pulses. A4, A5 and A6 data

bus pins are the outputs of A1, A2 and A3 shift

registers respectively.

The maximum frequency of the shift clock is

40MHz. This leads to an equivalent 240MHz serial

shift register for a 6 x 16 bits arrangement.

When the STB signal is Low, data are transferred

from the shift register to the latch and the power

output stages.

All the output data are kept memorised and held in

the latch stage when the latch input STB is pulled

high.

Vsssub and Vsslog must be connected as close as

possible to the logical reference ground of the ap-

plication.

STV7620M is supplied with a 5 volt power supply.

All the logic inputs can be driven either by 5V

CMOS logic or by 3.3 V CMOS logic.

A low EMI function has been implemented: the fall-

ing edge of the outputs has 2 slopes, a smooth

one for 30ns followed by a steeper one.

Table 1: Shift register truth table

Table 2: Power output truth table

Pn+1 = A1, Pn+2 = A2, Pn+3 = A3, Pn+4 = A4, Pn+5 = A5, Pn+6 = A6, n = [0,6,12,18,...,90]

and BS = “L”

Input

Shift register function

BS

F/R

CLK

Output Q

X

L

rise

Forward shift

X

L

H or L

Steady

X

H

rise

Reverse shift

X

H

H or L

Steady

H

X

X

3 bits shift register

L

X

X

6 bits shift register

Pn

STB

BLK

POC

Driver Output

Comments

X

X

L

X

all L

Output at low level

X

X

H

L

all H

Output at high level

X

H

H

H

Qn

Data latched

L

L

H

H

L

Data copied

H

L

H

H

H

Data copied