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ADE3000 数据表(PDF) 77 Page - STMicroelectronics |
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ADE3000 数据表(HTML) 77 Page - STMicroelectronics |
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77 / 88 page  77/88 ADE3XXX Pulse Width Modulation (PWM) Block 2.24 Pulse Width Modulation (PWM) Block The PWM B block generates two signals to control backlight inverter switching power components directly. It is derived from XCLK and powered up independently of the DOTCLK and INCLK domains. Frequency, duty cycle, polarity and overlap/non-overlap are programmable. The output frequency can “free-run” or lock to output vsync. OMUX_ DLY_GB4 0x0C3E R/W [7:4] 0x0 Delay for OGB5 R/W [3:0] 0x0 Delay for OGB4 OMUX_ DLY_GB6 0x0C3D R/W [7:4] 0x0 Delay for OGB7 R/W [3:0] 0x0 Delay for OGB6 OMUX_ DLY_RB0 0x0C3C R/W [7:4] 0x0 Delay for ORB1 R/W [3:0] 0x0 Delay for ORB0 OMUX_ DLY_RB2 0x0C3B R/W [7:4] 0x0 Delay for ORB3 R/W [3:0] 0x0 Delay for ORB2 OMUX_ DLY_R_B4 0x0C3A R/W [7:4] 0x0 Delay for ORB5 R/W [3:0] 0x0 Delay for ORB4 OMUX_ DLY_R_B6 0x0C39 R/W [7:4] 0x0 Delay for ORB7 R/W [3:0] 0x0 Delay for ORB6 OMUX_ DLY_TCON_0 0x0C38 R/W [7:4] 0x0 Delay for TCON1 R/W [3:0] 0x0 Delay for TCON0 OMUX_ DLY_TCON_2 0x0C37 R/W [7:4] 0x0 Delay for TCON3 R/W [3:0] 0x0 Delay for TCON2 OMUX_ DLY_TCON_4 0x0C36 R/W [7:4] 0x0 Delay for TCON5 R/W [3:0] 0x0 Delay for TCON4 OMUX_ DLY_TCON_6 0x0C35 R/W [7:4] 0x0 Delay for TCON7 R/W [3:0] 0x0 Delay for TCON6 OMUX_ DLY_VS_ENAB 0x0C34 R/W [7:4] 0x0 Delay for VSYNC R/W [3:0] 0x0 Delay for ENAB OMUX_ DLY_CLK_HS 0x0C33 R/W [7:4] 0x0 Delay for CLK R/W [3:0] 0x0 Delay for HSYNC OMUX_CTRL_3 0x0C51 R/W [7:3] Reserved R/W [2] 0x0 PWM mux mode R/W [1] 0x0 PWM enable R/W [0] 0x0 TCON data invert enable, with computed data invert pin. OMUX_REFCOUNT 0x0C52 [7:6] Reserved R [5:0] 0x0 returns a value that indicates the ADE gate speed -- a function of temp and voltage higher = faster logic Table 29: Output Mux Registers (Sheet 3 of 3) Register Name Addr Mode Bits Default Description |
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