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ADE3000 数据表(PDF) 16 Page - STMicroelectronics

部件名 ADE3000
功能描述  LCD Display Engines with Integrated DVI, ADC and YUV Ports
PDF  88 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ADE3000 数据表(HTML) 16 Page - STMicroelectronics

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Global Control Block
ADE3XXX
16/88
GLBL_SCLK_SYNTH_CTRL
0x0009
[7:5]
0x0
Reserved
R/W
[4:3]
0x0
XTAL frequency multiplier NDIV
0x0: fXCLK = 54MHz
0x1: fXCLK = 27MHz (normal)
0x2: fXCLK = 13.5MHz
0x3: Reserved
R/W
[2]
0x0
SCLK frequency synthesizer EXT_PLL
(normal operation = 0)
R/W
[1]
0x0
SCLK frequency synthesizer PLL_SEL
(normal operation = 1)
R/W
[0]
0x1
SCLK freq synth control disable (normal
operation = 0)
GLBL_SCLK_MD_SD
0x000A
R/W
[7:3]
0x0
SCLK frequency synthesizer MD, range is
[16,31]
R/W
[2:0]
0x0
SCLK frequency synthesizer SDIV, range is
[0,7]
GLBL_SCLK_PE_L
0x000B
R/W
[7:0]
0x0
SCLK frequency synthesizer PE, range is [0,
32767]
GLBL_SCLK_PE_H
0x000C
R/W
[7:0]
GLBL_TST_CTRL
0x000D
[7:1]
0x0
Reserved
R/W
[0]
0x0
Functional Test Mode Enable
GLBL_ADC_CLK_SRC_SEL
[7:3]
Reserved
R/W
[2:0]
0x5
ADC Sample Clock Source
0x0: YUVCLK pin
0x1: LLK_PLL (normal)
0x2: SCLK freq synth
0x3: CLKIN pin
0x4: FM freq synth
0x5: Crystal Clock
0x6: 0
0x7: Reserved
GLBL_SCLK_CTRL
0x0010
[7:5]
0x0
Reserved
R/W
[4]
0x0
Invert SCLK
[3]
Reserved
R/W
[2:0]
0x0
SCLK source select
0x0: YUVCLK pin
0x1: SCLK freq synth
0x2: FM freq synth (normal)
0x3: inclk source
0x4: CLKIN pin
0x5: crystal clock
0x6: 0
0x7: Reserved
GLBL_TCON_BPAD_EN
0x0011
R/W
[7:0]
0x0
For each bit n (0 to 7),
0: TCON[n] pin is TCON output
1: TCON[n] pin is input into TVI block
Table 4: Global Registers (Sheet 3 of 4)
Register Name
Addr.
Mode
Bits
Default
Description



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