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ADE3XXX

Sync Mux Block

SMUX_CTRL2

0x0202

[7]

0x0

V_reference toggle output

R/W

[6]

0x0

Software odd set (for testing odd params on

the bench)

R/W

[5:4]

0x0

Odd_out select

0x0: YUV

0x1: v_reference toggle

0x2: SMUX_CTRL2[6]

0x3: Reserved

R/W

[3]

0x0

Valid_out select

0: YUV

1: valid_generated

R/W

[2]

0x0

Enab_out select

0: enab_internal

1: enab_generated

R/W

[1]

0x0

Vsync_out select

0: vsync_internal

1: hsync_generated

R/W

[0]

0x0

Hsync_out select

0: hsync_internal

1: hsync_generated

SMUX_CLAMP_SET_L

0x0203

R/W

[7:0]

0x0

ADC clamp signal rising edge [11:0], relative

to selected horizontal reference signal, in

INCLKs (pixels)

SMUX_CLAMP_SET_H

0x0204

R/W

[3:0]

0x0

SMUX_CLAMP_RST_L

0x0205

R/W

[7:0]

0x0

ADC clamp falling edge [11:0]

SMUX_CLAMP_RST_H

0x0206

R/W

[3:0]

0x0

SMUX_HENAB_SET_L

0x0207

R/W

[7:0]

0x0

Horizontal enable start [11:0] (left edge of

image) relative to the selected horizontal

reference edge in INCLKs (pixels))

SMUX_HENAB_SET_H

0x0208

R/W

[3:0]

0x0

SMUX_HENAB_RST_L

0x0209

R/W

[7:0]

0x0

Horizontal enable end [11:0]

SMUX_HENAB_RST_H

0x020A

R/W

[3:0]

0x0

SMUX_VENAB_SET_L

0x020B

R/W

[7:0]

0x0

Vertical enable start [11:0] (top edge of

image) relative to the selected vertical

reference edge (in lines)

SMUX_VENAB_SET_H

0x020C

R/W

[3:0]

0x0

SMUX_VENAB_RST_L

0x020D

R/W

[7:0]

0x0

Vertical enable end

SMUX_VENAB_RST_H

0x020E

R/W

[3:0]

0x0

SMUX_HSYNC_PHASE

0x020F

R/W

[7:0]

0x0

Number of horizontal pixels/INCLKs that the

generated hsync edge is from the horizontal

reference edge. 2’s complement

[-128,127]

SMUX_VSYNC_PHASE

0x0210

R/W

[7:0]

0x0

Number of vertical lines that the generated

vsync edge is from the vertical reference

edge. 2’s complement

[-128,127]

Table 14: Sync Mux Registers (Sheet 2 of 2)

Addr

Mode

Bits

Default

Description

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