© 2011 Microchip Technology Inc.

DS21743B-page 13

TC72

TABLE 4-3:

OPERATIONAL MODES

4.4

Read Operation

The TC72 uses the CE, SCK and SDO lines to output

the Temperature and Control register data. Figure 4-3

shows a timing diagram of the read operation.

Communication is initiated by the chip enable (CE)

going high. The SDO line remains at the voltage level

of the LSb bit that is output and goes to the tri-state

level when the CE line goes to a logic low level.

4.5

Write Operation

Data is clocked into the Control register in order to

enable TC72’s power saving shutdown mode. The

write operation is shown in Figure 4-3 and is

accomplished using the CE, SCK and SDI lines.

FIGURE 4-2:

Serial Clock Polarity (CP)

Operation.

Mode

CE

SCK (Note 1)SDI

SDO

Disable

L

Input Disabled

Input Disabled

High Z

Write (A7 = 1)H

CP=1, Data Shifted on Falling Edge,

Data Clocked on Rising Edge

Data Bit Latch

High Z

CP=0, Data Shifted on Rising Edge,

Data Clocked on Falling Edge

Read (A7 = 0)H

CP=1, Data Shifted on Falling Edge,

Data Clocked on Rising Edge

X

Next data bit shift,

Note 2

CP=0, Data Shifted on Rising Edge,

Data Clocked on Falling Edge

Note 1:

CP is the Clock Polarity of the microcontroller system clock. If the inactive state of SCK is logic level high,

CP is equal to ‘1’; otherwise, if the inactive state of SCK is low, CP is equal to ‘0’.

2:

During a Read operation, SDO remains at a high impedance (High Z) level until the eight bits of data begin

to be shifted out of the Temperature register.

SHIFT

EDGE

CLOCK

EDGE

SHIFT

EDGE

CLOCK

EDGE

SCK

CE

CE

SCK

CP = 0

CP = 1