P89LPC930 datasheet(39/55 Pages) PHILIPS

39 / 55 page

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Product data

Rev. 05 — 15 December 2004

39 of 55

9397 750 14472

addition, erasing and reprogramming of user-programmable bytes including UCFG1,

the Boot Status Bit, and the Boot Vector is supported. As shipped from the factory,

the upper 512 bytes of user code space contains a serial In-System Programming

(ISP) routine allowing for the device to be programmed in circuit through the serial

port.

Flash programming and erasing: There are three methods of erasing or

programming of the Flash memory that may be used. First, the Flash may be

programmed or erased in the end-user application by calling low-level routines

through a common entry point. Second, the on-chip ISP boot loader may be invoked.

This ISP boot loader will, in turn, call low-level routines through the same common

entry point that can be used by the end-user application. Third, the Flash may be

programmed or erased using the parallel method by using a commercially available

EPROM programmer which supports this device. This device does not provide for

direct veriﬁcation of code memory contents. Instead this device provides a 32-bit

CRC result on either a sector or the entire 8 kbytes of user code space.

Boot ROM: When the microcontroller programs its own Flash memory, all of the low

level details are handled by code that is contained in a Boot ROM that is separate

from the Flash memory. A user program simply calls the common entry point in the

Boot ROM with appropriate parameters to accomplish the desired operation. The

Boot ROM include operations such as erase sector, erase page, program page, CRC,

program security bit, etc. The Boot ROM occupies the program memory space at the

top of the address space from FF00 to FEFF hex, thereby not conﬂicting with the user

program memory space.

Power-on reset code execution: The P89LPC930/931 contains two special Flash

elements: the Boot Vector and the Boot Status Bit. Following reset, the

P89LPC930/931 examines the contents of the Boot Status Bit. If the Boot Status Bit

is set to zero, power-up execution starts at location 0000H, which is the normal start

address of the user’s application code. When the Boot Status Bit is set to a value

other than zero, the contents of the Boot Vector is used as the high byte of the

execution address and the low byte is set to 00H. The factory default setting is 01EH

(0EH for the LPC930), corresponds to the address 1E00H (0E00h for the LPC930) for

the default ISP boot loader. This boot loader is pre-programmed at the factory into

this address space and can be erased by the user. Users who wish to use this

loader should take cautions to avoid erasing the 1 kbyte sector from 1C00H to

1FFFH (0C00H to 0FFFH for the LPC930). Instead, the page erase function can

be used to erase the eight (four for the LPC930) 64-byte pages located from

1C00H to 1DFFH (0C00H to 0DFFH for the LPC930). A custom boot loader can be

written with the Boot Vector set to the custom boot loader, if desired.

Hardware activation of the boot loader: The boot loader can also be executed by

forcing the device into ISP mode during a power-on sequence (see the

P89LPC930/931 User’s Manual for speciﬁc information). This has the same effect as

having a non-zero status byte. This allows an application to be built that will normally

execute user code but can be manually forced into ISP operation. If the factory default

setting for the Boot Vector (1EH for the lPC931, 0EH for the LPC930) is changed, it

will no longer point to the factory pre-programmed ISP boot loader code. If this

happens, the only way it is possible to change the contents of the Boot Vector is

through the parallel programming method, provided that the end user application

does not contain a customized loader that provides for erasing and reprogramming of

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