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LM4921 数据表(PDF) 7 Page - National Semiconductor (TI) |
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LM4921 数据表(HTML) 7 Page - National Semiconductor (TI) |
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7 / 18 page ![]() Electrical Characteristics-Digital Inputs DV DD = 3.0V (Notes 1, 2) The following specifications apply for the circuit shown in Figure 1 unless otherwise specified. Limits apply for T A = 25˚C. Symbol Parameter Conditions LM4921 Units (Limits) Typical Limit (Note 6) (Notes 7, 9) Resolution 16 Bits I 2S Audio Data Interface Format Standard, I 2S, Left Justified f MCLK Master Clock Frequency 11.2896 (256FS) MHz f CONV Sampling Clock Frequency Range 44.1 48 kHz V IL Digital Input: Logic Low Voltage Level 0.3XDV DD V (max) V IH Digital Input: Logic High Voltage Level 0.7XDV DD V (min) t ES SPI_ENB Setup Time 20 ns (min) t EH SPI_ENB Hold Time 20 ns (min) t EL SPI_ENB Low Time 30 ns (min) t DS SPI_Data Setup Time 20 ns (min) t DH SPI_Data Hold Time 20 ns (min) t CS SPI_CLK Setup Time 20 ns (min) t CH SPI_CLK High Pulse Width 100 ns (min) t CL SPI_CLK Low Pulse Width 100 ns (min) f CLK SPI_CLK Frequency 5 MHz (max) t CLKI2SI 2S_CLK Period 50 ns (min) t HII2SI 2S_CLK High Pulse Width 20 ns (min) t LOI2S I 2S_CLK Low Pulse Width 20 ns (min) I 2S_LRCLK Duty Cycle 50 % t SLRCLK I 2S_LRCLK to I2S_CLK Setup Time 20 ns (min) t HLRCLK I 2S_LRCLK to I2S_CLK Hold Time 20 ns (min) t SDI2SI 2S_Data to I2S_CLK Setup Time 20 ns (min) t HDI2SI 2S_Data to I2S_CLK Hold Time 20 ns (min) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature TA. The maximum allowable power dissipation is PDMAX =(TJMAX–TA)/θJA or the number given in Absolute Maximum Ratings, whichever is lower. Note 4: Human body model, 100pF discharged through a 1.5k Ω resistor. Note 5: Machine Model, 220pF – 240pF discharged through all pins. Note 6: Typicals are measured at 25˚C and represent the parametric norm. Note 7: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Best operation is achieved by maintaining 3.0V ≤ AVDD ≤ 5.0V and 3.0V ≤ DVDD ≤ 5.0V. Note 9: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. www.national.com 7 |
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