SPI TIMING DIAGRAM

200486G1

SPI OPERATIONAL REQUIREMENTS

1. The maximum clock rate is 5MHz for the CLK pin.

2. CLK must remain logic-high for at least 100ns (t

the rising edge of CLK, and CLK must remain logic-low for at

least 100ns (t

3. Data bits are written to the DATA pin with the least

significant bit (LSB) first.

4. The serial data bits are sampled at the rising edge of CLK.

Any transition on DATA must occur at least 20ns (t

the rising edge of CLK. Also, any transition on DATA must

occur at least 20ns (t

stabilize before the next rising edge of CLK.

5. ENABLE should be logic-high only during serial data

transmission.

6. ENABLE must be logic-high at least 20ns (t

first rising edge of CLK, and ENABLE has to remain logic-

high at least 20ns (t

CLK.

7. If ENABLE remains logic-low for more than 10ns before all

16 bits are transmitted then the data latch will be aborted.

8. If ENABLE is logic-high for more than 16 CLK pulses then

only the first 16 data bits will be latched and activated at

rising edge of sixteenth CLK.

9. ENABLE must remain logic-low for at least 30ns (t

10. Coincidental rising or falling edges of CLK and ENABLE

are not allowed. If CLK is to be held logic-high after the data

transmission, the falling edge of CLK must occur at least

20ns (t

next set of data.

I2S INTERFACE BUS (J2 - Fig 2)

The I2S standard provides a uni-directional serial interface

designed specifically for digital audio. For the LM4921, the

interface provides access to a 48kHz, 16 bit full-range stereo

audio DAC. This interface uses a three wire system of clock

(I2S_CLK), data (I2S_DATA), and word select (I2S_WS,

sometimes called Right/Left Select).

A bit clock (I2S_CLK) at 32 or 64 times the sample frequency

is established by the I2S system master and the word select

(I2S_WS) line is driven at a frequency equal to the sampling

rate of the audio data, in this case 48kHz. The word line is

registered to change on the positive edge of the bit clock.

The serial data (I2S_DATA) is sent MSB first, again registers

on the positive edge of the bit clock, delayed by 1 bit clock

cycle relative to the changing of the word line (typical I

format).

MCLK/XTAL_IN (S1 MCLK SEL - Fig 2)

This is the input for an external Master Clock. The jumper at

S1 must be removed (disconnecting the onboard crystal

from the circuit) when using an external Master Clock.

STEREO HEADPHONE OUTPUT JACK (J3 - Fig 2)

This is the stereo headphone output. Each channel is single-

ended, with 100uF DC output blocking capacitors mounted

on the demo board (C6 and C7). These capacitors are

necessary to block the 1/2 VDD DC bias and prevent it from

flowing through the headphone speakers (DC current will

destroy most audio speakers) while allowing the audio ac

signal to pass through. The jack features a typical stereo

headphone pinout.

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