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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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OMAP3530ECBBA 数据表(PDF) 157 Page - Texas Instruments |
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OMAP3530ECBBA 数据表(HTML) 157 Page - Texas Instruments |
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157 / 265 page  OMAP3530, OMAP3525 www.ti.com SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode (continued) NO. PARAMETER 1.15 V 1.0 V 0.9 V UNIT MIN MAX MIN MAX MIN MAX tj(CLK) Jitter standard 33.3 33.3 33.3 ps deviation(16), output clock gpmc_clk tR(CLK) Rise time, output clock 1.6 2 2 ns gpmc_clk tF(CLK) Fall time, output clock 1.6 2 2 ns gpmc_clk tR(DO) Rise time, output data 2 2 2 ns tF(DO) Fall time, output data 2 2 2 ns F2 td(CLKH-nCSV) Delay time, gpmc_clk F(6) – 1.9 F(6) + 3.3 F(6) – 1.8 F(6) + 4.1 F(6) – 2.6 F(6) + 4.9 ns rising edge to gpmc_ncsx(11) transition F3 td(CLKH-nCSIV) Delay time, gpmc_clk E(5) – 1.9 E(5) + 3.3 E(5) – 1.8 E(5) + 4.1 E(5) – 2.6 E(5) + 4.9 ns rising edge to gpmc_ncsx(11) invalid F4 td(ADDV-CLK) Delay time, address bus B(2) – 4.1 B(2) + 2.1 B(2) – 4.1 B(2) + 2.1 B(2) – 4.9 B(2) + 2.6 ns valid to gpmc_clk first edge F5 td(CLKH-ADDIV) Delay time, gpmc_clk –2.1 –2.1 –2.6 ns rising edge to gpmc_a[16:1] invalid F6 td(nBEV-CLK) Delay time, B(2) – 1.1 B(2) + 2.1 B(2) – 0.9 B(2) + 1.9 B(2) – 2.6 B(2) + 2.6 ns gpmc_nbe0_cle, gpmc_nbe1 valid to gpmc_clk first edge F7 td(CLKH-nBEIV) Delay time, gpmc_clk D(4) – 2.1 D(4) + 1.1 D(4) – 1.9 D(4) + 0.9 D(4) – 2.6 D(4) + 2.6 ns rising edge to gpmc_nbe0_cle, gpmc_nbe1 invalid F8 td(CLKH-nADV) Delay time, gpmc_clk G(7) – 1.9 G(7) + 4.1 G(7) – 2.1 G(7) + 4.1 G(7) – 2.6 G(7) + 4.9 ns rising edge to gpmc_nadv_ale transition F9 td(CLKH-nADVIV) Delay time, gpmc_clk D(4) – 1.9 D(4) + 4.1 D(4) – 2.1 D(4) + 4.1 D(4) – 2.6 D(4) + 4.9 ns rising edge to gpmc_nadv_ale invalid F10 td(CLKH-nOE) Delay time, gpmc_clk H(8) – 2.1 H(8) + 2.1 H(8) – 2.1 H(8) + 2.1 H(8) – 2.6 H(8) + 4.9 ns rising edge to gpmc_noe transition F11 td(CLKH-nOEIV) Delay time, gpcm rising E(5) – 2.1 E(5) + 2.1 E(5) – 2.1 E(5) + 2.1 E(5) – 2.6 E(5) + 4.9 ns edge to gpmc_noe invalid F14 td(CLKH-nWE) Delay time, gpmc_clk I(9) – 1.9 I(9) + 4.1 I(9) – 2.1 I(9) + 4.1 I(9) – 2.6 I(9) + 4.9 ns rising edge to gpmc_nwe transition F15 td(CLKH-Data) Delay time, gpmc_clk J(10) – 2.1 J(10) + 1.1 J(10) – 1.9 J(10) + 0.9 J(10) – 2.6 J(10) + 2.6 ns rising edge to data bus transition F17 td(CLKH-nBE) Delay time, gpmc_clk J(10) – 2.1 J(10) + 1.1 J(10) – 1.9 J(10) + 0.9 J(10) – 2.6 J(10) + 2.6 ns rising edge to gpmc_nbex_cle transition F18 tW(nCSV) Pulse duration, Read A(1) A(1) A(1) ns gpmc_ncsx(11) Write A(1) A(1) A(1) ns low F19 tW(nBEV) Pulse duration, Read C(3) C(3) C(3) ns gpmc_nbe0_cle, Write C(3) C(3) C(3) ns gpmc_nbe1 low F20 tW(nADVV) Pulse duration, Read K(13) K(13) K(13) ns gpmc_nadv_ale Write K(13) K(13) K(13) ns low Copyright © 2008–2013, Texas Instruments Incorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 157 Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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