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OMAP3530ECBBA 数据表(PDF) 227 Page - Texas Instruments |
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OMAP3530ECBBA 数据表(HTML) 227 Page - Texas Instruments |
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227 / 265 page  hsusbx_tll_clk hsusbx_tll_stp hsusbx_tll_dir_&_nxt hsusbx_tll_data[3:0] Data_IN Data_IN_(n+1) Data_IN_(n+2) Data_OUT Data_OUT_(n+1) HSU0 HSU6 HSU2 HSU3 HSU6 HSU1 HSU1 HSU4 HSU4 HSU5 HSU5 HSU7 HSU8 HSU7 030-089 OMAP3530, OMAP3525 www.ti.com SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 Table 6-106. High-Speed USB Switching Characteristics – 8-bit TLL Master Mode(1) NO. PARAMETER 1.15 V UNIT MIN MAX HSU0 fp(CLK) hsusbx_tll_clk clock frequency 60 MHz tj(CLK) Jitter standard deviation(2), hsusbx_tll_clk 200 ps HSU1 tj(CLK) Duty cycle, hsusbx_tll_clk pulse duration (low and high) 47.6% 52.4% HSU6 td(CLKL-DIRV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid 9 ns td(CLKL-DIRIV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid 0 ns td(CLKL-NXTV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid 9 ns td(CLKL-NXTIV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid 0 ns HSU7 td(CLKL-DV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] valid 4 ns HSU8 td(CLKL-DIV) Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] invalid 0 ns tR(do) Rise time, output signals 2 ns tF(do) Fall time, output signals 2 ns (1) In hsusbx, x is equal to 1, 2, or 3. (2) The jitter probability density can be approximated by a Gaussian function. In hsusbx, x is equal to 1, 2, or 3. Figure 6-52. High-Speed USB – 8-bit TLL Master Mode Copyright © 2008–2013, Texas Instruments Incorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 227 Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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