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OMAP3530ECBBA 数据表(PDF) 148 Page - Texas Instruments |
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OMAP3530ECBBA 数据表(HTML) 148 Page - Texas Instruments |
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148 / 265 page  OMAP Device DSS tv_vref DIN1[9:0] vssa_dac vdda_dac VideoDAC 1 TVDCT VideoDAC 2 TVOUT BUFFER DIN2[9:0] TVOUT BUFFER TVOUT BUFFER tv_vfb1 tv_out1 CBG tv_out2 tv_vfb2 V_ref 030-018 OMAP3530, OMAP3525 SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 www.ti.com 5 VIDEO DAC SPECIFICATIONS A dual-display interface equips the OMAP3530/25 processor. This display subsystem provides the necessary control signals to interface the memory frame buffer directly to the external displays (TV-set). Two (one per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to generate the video analog signal. One of the video DACs also includes TV detection and power-down mode. Figure 5-1 illustrates the OMAP3530/25 DAC architecture. For more information, see the DSS chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]. Figure 5-1. Video DAC Architecture The following paragraphs detail the 10-bit DAC interface pinout, static and dynamic specifications, and noise requirements. The operating conditions and absolute maximum ratings are detailed in Table 5-2 and Table 5-4. 5.1 Interface Description Table 5-1 summarizes the external pins of the video DAC. Table 5-1. External Pins of 10-bit Video DAC PIN NAME I/O DESCRIPTION tv_out1 O TV analog output composite DAC1 video output. An external resistor is connected between this node and tv_vfb1. The nominal value of ROUT1 is 1650 Ω. Finally, note that this is the output node that drives the load (75 Ω). 148 VIDEO DAC SPECIFICATIONS Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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