 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
OMAP3530ECBBA 数据表(PDF) 146 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
OMAP3530ECBBA 数据表(HTML) 146 Page - Texas Instruments |
|
|
146 / 265 page  OMAP3530, OMAP3525 SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 www.ti.com Table 4-18. DPLL3 Clock Frequency Ranges, VDD2 OPP2 (continued) Config 1 Config 2 (83 MHz) (100 MHz) Unit Clock Signal Description Min Max Min Max Output of clock manager (CM), generated using CM: L4_ICLK - 41.5 - 50 MHz CM L3_ICLK and divider. SGX SGX input clock, taken from CM CORE_CLK. - 55.53 - 66.67 MHz SDRC SDRC input clock, taken from CM L3_ICLK. - 83 - 100 MHz GPMC GPMC input clock, taken from CM L3_ICLK. - 41.5 - 50 MHz Table 4-19. DPLL3 Clock Frequency Ranges, VDD2 OPP1(1) Config 1 Config 2 (40 MHz) (50 MHz) Unit Clock Signal Description Min Max Min Max Output of clock manager (CM), generated directly CM: CORE_CLK - 83 - 100 MHz from DPLL3. Output of clock manager (CM), generated using CM: L3_ICLK - 41.5 - 50 MHz DPLL3. Output of clock manager (CM), generated using CM CM: L4_ICLK - 20.75 - 25 MHz L3_ICLK and divider. SGX SGX input clock, taken from CM CORE_CLK. - N/A - N/A MHz SDRC SDRC input clock, taken from CM L3_ICLK. - 41.5 - 50 MHz GPMC GPMC input clock, taken from CM L3_ICLK. - 41.5 - 25 MHz (1) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1. Table 4-20 summarizes the DLL characteristics. Table 4-20. DLL Characteristics PARAMETER MIN NOM MAX UNIT COMMENTS Supply voltage vdds_dpll_dll 1.71 1.8 1.89 V Junction operating temperature –40 25 105 °C Input clock frequency 66 120 133 MHz APPLICATION MODE 0 83 120 166 APPLICATION MODE 1 Input load(1) 15 fF Lock time(2) 500 Clocks Relock time 500 ns IDLE to MODEMAXDELAY (Mode transitions through idle mode) 150 372 Clocks IDLE to APPLICATION MODE 1 or 0 1 2 μs IDLE to APPLICATION MODE @133 MHz 1 1.5 μs IDLE to APPLICATION MODE @166 MHz (1) This parameter is design goal and is not tested on silicon. (2) Lock signal would go high from power down within 500 clocks. Lock signal switches to low state when the input clock is switched off after 3 μs. 146 CLOCK SPECIFICATIONS Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
