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OMAP3530ECBC 数据表(PDF) 225 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 225 Page - Texas Instruments |
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225 / 265 page ![]() hsusbx_clk hsusbx_stp hsusbx_dir_&_nxt hsusbx_data[7:0] Data_OUT Data_IN HSU1 HSU0 HSU1 HSU4 HSU2 HSU2 HSU6 HSU3 HSU5 030-087 OMAP3530, OMAP3525 www.ti.com SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 Table 6-100. High-Speed USB Switching Characteristics – 12-bit Master Mode(1) (continued) N O. PARAMETER 1.15 V UNIT MIN MAX td(clkL-DIV) Delay time, hsusbx_clk high to output hsusbx_data[0:7] invalid 2 ns tR(do) Rise time, output signals 2 ns tF(do) Fall time, output signals 2 ns In hsusbx, x is equal to 1 or 2. Figure 6-50. High-Speed USB – 12-bit Master Mode 6.6.4.3 High-Speed Universal Serial Bus (USB) on Ports 1, 2, and 3 – 12-bit TLL Master Mode Table 6-102 and Table 6-103 assume testing over the recommended operating conditions (see Figure 6- 51). Table 6-101. High-Speed USB Timing Conditions – 12-bit TLL Master Mode TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 2 ns tF Input signal fall time 2 ns Output Conditions CLOAD Output load capacitance 3 pF Table 6-102. High-Speed USB Timing Requirements – 12-bit TLL Master Mode(1) NO. PARAMETER 1.15 V UNIT MIN MAX HSU2 ts(STPV-CLKH) Setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge 6 ns HSU3 ts(CLKH-STPIV) Hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge 0 ns HSU4 ts(DATAV-CLKH) Setup time, hsusbx_tll_data[7:0] valid before hsusbx_tll_clk rising edge 6 ns HSU5 th(CLKH-DATIV) Hold time, hsusbx_tll_data[7:0] valid after hsusbx_tll_clk rising edge 0 ns (1) In hsusbx, x is equal to 1, 2, or 3. Table 6-103. High-Speed USB Switching Characteristics – 12-bit TLL Master Mode(1) NO. PARAMETER 1.15 V UNIT MIN MAX HSU0 fp(CLK) hsusbx_tll_clk clock frequency 60 MHz (1) In hsusbx, x is equal to 1, 2, or 3. Copyright © 2008–2013, Texas Instruments Incorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 225 Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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