OMAP3530ECBC datasheet(228/265 Pages) TI1

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OMAP3530, OMAP3525

SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013

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6.6.5

2C Interface

The multimaster I2C peripheral provides an interface between two or more devices via an I2C serial bus.

The I2C controller supports the multimaster mode which allows more than one device capable of

controlling the bus to be connected to it. Each I2C device is recognized by a unique address and can

operate as either transmitter or receiver, according to the function of the device. In addition to being a

transmitter or receiver, a device connected to the I2C bus can also be considered as master or slave when

performing data transfers. This data transfer is carried out via two serial bidirectional wires:

•

An SDA data line

•

An SCL clock line

The following sections illustrate the data transfer is in master or slave configuration with 7-bit addressing

format. The I2C interface is compliant with Philips I2C specification version 2.1. It supports standard mode

(up to 100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s) .

6.6.5.1

I2C Standard/Fast-Speed Mode

Table 6-107. I2C Standard/Fast-Speed Mode Timings

NO.

PARAMETER(1)

Standard Mode

Fast Mode

UNIT

MIN

MAX

MIN

MAX

fSCL

Clock Frequency, i2cX_scl

100

400

kHz

tw(SCLH)

Pulse Duration, i2cX_scl high

0.6

μs

tw(SCLL)

Pulse Duration, i2cX_scl low

4.7

1.3

μs

tsu(SDAV-SCLH)

Setup time, i2cX_sda valid before i2cX_scl active level

250

100(2)

th(SCLH–SDAV)

Hold time, i2cX_sda valid after i2cX_scl active level

0(3)

3.45(4)

0(3)

0.9(4)

μs

tsu(SDAL-SCLH)

Setup time, i2cX_scl high after i2cX_sda low (for a

4.7

0.6

μs

START(5) condition or a repeated START condition)

th(SCLH–SDAH)

Hold time, i2cX_sda low level after i2cX_scl high level

0.6

μs

(STOP condition)

th(SCLH–RSTART)

Hold time, i2cX_sda low level after i2cX_scl high level (for

0.6

μs

a repeated START condition)

tw(SDAH)

Pulse duration, i2cX_sda high between STOP and START

4.7

1.3

μs

conditions

tR(SCL)

Rise time, i2cX_scl

1000

300

tF(SCL)

Fall time, i2cX_scl

300

tR(SDA)

Rise time, i2cX_sda

1000

300

tF(SDA)

Fall time, i2cX_sda

300

Capacitive load for each bus line

60(6)

(1)

In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.

(2)

A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDAV-SCLH) ≥ 250 ns must then be

met. This is automatically the case if the device does not stretch the low period of the i2cx_scl. If such a device does stretch the low

period of the i2cx_scl, it must output the next data bit to the i2cx_sda line tr(SDA) max + tsu(SDAV-SCLH) = 1000 + 250 = 1250 ns (according

to the standard-mode I2C-bus specification) before the i2cx_scl line is released.

(3)

The device provides (via the I2C bus) a hold time of at least 300 ns for the i2cx_sda signal (see the fall and rise time of i2cx_scl) to

bridge the undefined region of the falling edge of i2cx_scl.

(4)

The maximum th(SCLH-SDA) has only to be met if the device does not stretch the low period of the i2cx_scl signal.

(5)

After this time, the first clock is generated.

(6)

Maximum reference load for i2c4_scl and i2c4_sda is CB = 15 pF.

228

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

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