OMAP3530ECBC datasheet(231/265 Pages) TI1

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HDQ

tHW 1

tHW 0

tCYCH

030-096

HDQ

tBR

030-095

OMAP3530, OMAP3525

www.ti.com

SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013

Table 6-109. Correspondence Standard vs. TI Timing References (continued)

TI-OMAP

STANDARD-I2C

S/F Mode

HS Mode

th(SCLH-RSTART)

TSU;STO

tw(SDAH)

TBUF

6.6.6

HDQ / 1-Wire Interfaces

This module is intended to work with both the HDQ and the 1-Wire protocols. The protocols use a single

wire to communicate between the master and the slave. The protocols employ an asynchronous return to

1 mechanism where, after any command, the line is pulled high.

6.6.6.1

HDQ Protocol

Table 6-110 and Table 6-111 assume testing over the recommended operating conditions (see Figure 6-

55 through Figure 6-58).

Table 6-110. HDQ Timing Requirements

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

tCYCD

Bit window

253

μs

tHW1

tHW0

180

tRSPS

Command to host respond time(1)

(1)

Defined by software.

Table 6-111. HDQ Switching Characteristics

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Break timing

193

μs

tBR

Break recovery

tCYCH

Bit window

253

tDW1

Sends1 (write)

1.3

tDW0

Sends0 (write)

101

Figure 6-55. HDQ Break (Reset) Timing

Figure 6-56. HDQ Read Bit Timing (Data)

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

231

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