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OMAP3530ECBC 数据表(PDF) 238 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 238 Page - Texas Instruments |
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238 / 265 page  OMAP3530, OMAP3525 SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 www.ti.com Table 6-123. MMC/SD/SDIO Timing Requirements – High-Speed MMC Mode(1) (2) (3) (4) (continued) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX MMC/SD/SDIO Interface 1 (3.0 V IO) MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before mmc1_clk 5.6 26 ns rising clock edge MMC4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk 2.3 1.9 ns rising clock edge MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before mmc1_clk 5.6 26 ns rising clock edge MMC8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk 2.3 1.9 ns rising clock edge MMC/SD/SDIO Interface 2 MMC3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before mmc2_clk 5.6 26 ns rising clock edge MMC4 tsu(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk 2.3 1.9 ns rising clock edge MMC7 tsu(DATxV-CLKIH) Setup time, mmc2_datx valid before mmc2_clk 5.6 26 ns rising clock edge MMC8 tsu(CLKIH-DATxIV) Hold time, mmc2_datx valid after mmc2_clk 2.3 1.9 ns rising clock edge MMC/SD/SDIO Interface 3 MMC3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before mmc3_clk 5.6 26 ns rising clock edge MMC4 tsu(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk 2.3 1.9 ns rising clock edge MMC7 tsu(DATxV-CLKIH) Setup time, mmc3_datx valid before mmc3_clk 5.6 26 ns rising clock edge MMC8 tsu(CLKIH-DATxIV) Hold time, mmc3_datx valid after mmc3_clk 2.3 1.9 ns rising clock edge Table 6-124. MMC/SD/SDIO Switching Characteristics – High-Speed MMC Mode(1) N O. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX High-Speed MMC Mode 1/MMC 1/tc(clk) Frequency(2), mmcx_ clk (3) 48 24 MHz 1 MMC2 tW(clkH) Typical pulse duration, output clk high X(4)*PO(5) X(4)*PO(5) ns MMC2 tW(clkL) Typical pulse duration, output clk low Y(6)*PO(5) Y(6)*PO(5) ns tdc(clk) Duty cycle error, output clk 1041.7 2083.3 ps tj(clk) Jitter standard deviation(3), output clk 200 200 ps MMC/SD/SDIO Interface 1 (1.8 V IO) tc(clk) Rise time, output clk 3 3 ns tW(clkH) Fall time, output clk 3 3 ns tW(clkL) Rise time, output data 3 3 ns tdc(clk) Fall time, output data 3 3 ns MMC5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to 3.7 14.1 4.1 34.5 ns mmc1_cmd transition (1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. (2) Related with the output clk maximum and minimum frequencies programmable in I/F module. (3) In mmcx_clk, 'x' is equal to 1, 2, or 3. (4) The X parameter is defined as shown in Table 6-125. (5) PO = output clk period in ns. (6) The Y parameter is defined as shown in Table 6-126. 238 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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