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OMAP3530ECBC 数据表(PDF) 241 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 241 Page - Texas Instruments |
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241 / 265 page  OMAP3530, OMAP3525 www.ti.com SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 Table 6-128. MMC/SD/SDIO Timing Requirements – Standard MMC Mode and MMC Identification Mode(1) (2) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX Standard MMC Mode and MMC Identification Mode MMC/SD/SDIO Interface 1 (1.8 V IO) MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before 13.6 65.7 ns mmc1_clk rising clock edge MMC4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk 8.9 8.9 ns rising clock edge MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before 13.6 65.7 ns mmc1_clk rising clock edge MMC8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk 8.9 8.9 ns rising clock edge MMC/SD/SDIO Interface 1 (3.0 V IO) MMC3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before 13.6 65.7 ns mmc1_clk rising clock edge MMC4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk 8.9 8.9 ns rising clock edge MMC7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before 13.6 65.7 ns mmc1_clk rising clock edge MMC8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk 8.9 8.9 ns rising clock edge MMC/SD/SDIO Interface 2 MMC3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before 13.6 65.7 ns mmc2_clk rising clock edge MMC4 tsu(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk 8.9 8.9 ns rising clock edge MMC7 tsu(DATxV-CLKIH) Setup time, mmc2_datx valid before 13.6 65.7 ns mmc2_clk rising clock edge MMC8 tsu(CLKIH-DATxIV) Hold time, mmc2_datx valid after mmc2_clk 8.9 8.9 ns rising clock edge MMC/SD/SDIO Interface 3 MMC3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before 13.6 65.7 ns mmc3_clk rising clock edge MMC4 tsu(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk 8.9 8.9 ns rising clock edge MMC7 tsu(DATxV-CLKIH) Setup time, mmc3_datx valid before 13.6 65.7 ns mmc3_clk rising clock edge MMC8 tsu(CLKIH-DATxIV) Hold time, mmc3_datx valid after mmc3_clk 8.9 8.9 ns rising clock edge (1) Timing parameters are referred to output clock specified in Table 6-129. (2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-129. Table 6-129. MMC/SD/SDIO Switching Characteristics – Standard MMC Mode and MMC Identification Mode NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX MMC Identification Mode 1/MMC 1/tc(clk) Frequency(1), mmcx_ clk (2) 0.4 0.4 MHz 1 MMC2 tW(clkH) Typical pulse duration, output clk high X(3)*PO(4) X(3)*PO(4) ns (1) Related with the output clk maximum and minimum frequencies programmable in I/F module. (2) In mmcx_clk, 'x' is equal to 1, 2, or 3. (3) The X parameter is defined as shown in Table 6-130. (4) PO = output clk period in ns. Copyright © 2008–2013, Texas Instruments Incorporated TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS 241 Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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