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OMAP3530ECBC 数据表(PDF) 244 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 244 Page - Texas Instruments |
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244 / 265 page  OMAP3530, OMAP3525 SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 www.ti.com Table 6-133. MMC/SD/SDIO Timing Requirements – High-Speed SD Mode(1) (2) (3) NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX High-Speed SD Mode MMC/SD/SDIO Interface 1 (1.8 V IO) HSSD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before 5.6 26 ns mmc1_clk rising clock edge HSSD4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk 2.3 1.9 ns rising clock edge HSSD7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before 5.6 26 ns mmc1_clk rising clock edge HSSD8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk 2.3 1.9 ns rising clock edge MMC/SD/SDIO Interface 1 (3.0 V IO) HSSD3 tsu(CMDV-CLKIH) Setup time, mmc1_cmd valid before 5.6 26 ns mmc1_clk rising clock edge HSSD4 tsu(CLKIH-CMDIV) Hold time, mmc1_cmd valid after mmc1_clk 2.3 1.9 ns rising clock edge HSSD7 tsu(DATxV-CLKIH) Setup time, mmc1_datx valid before 5.6 26 ns mmc1_clk rising clock edge HSSD8 tsu(CLKIH-DATxIV) Hold time, mmc1_datx valid after mmc1_clk 2.3 1.9 ns rising clock edge MMC/SD/SDIO Interface 2 HSSD3 tsu(CMDV-CLKIH) Setup time, mmc2_cmd valid before 5.6 26 ns mmc2_clk rising clock edge HSSD4 tsu(CLKIH-CMDIV) Hold time, mmc2_cmd valid after mmc2_clk 2.3 1.9 ns rising clock edge HSSD7 tsu(DATxV-CLKIH) Setup time, mmc2_datx valid before 5.6 26 ns mmc2_clk rising clock edge HSSD8 tsu(CLKIH-DATxIV) Hold time, mmc2_datx valid after mmc2_clk 2.3 1.9 ns rising clock edge MMC/SD/SDIO Interface 3 HSSD3 tsu(CMDV-CLKIH) Setup time, mmc3_cmd valid before 5.6 26 ns mmc3_clk rising clock edge HSSD4 tsu(CLKIH-CMDIV) Hold time, mmc3_cmd valid after mmc3_clk 2.3 1.9 ns rising clock edge HSSD7 tsu(DATxV-CLKIH) Setup time, mmc3_datx valid before 5.6 26 ns mmc3_clk rising clock edge HSSD8 tsu(CLKIH-DATxIV) Hold time, mmc3_datx valid after mmc3_clk 2.3 1.9 ns rising clock edge (1) Timing Parameters are referred to output clock specified in Table 6-134. (2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-134. (3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7. Table 6-134. MMC/SD/SDIO Switching Characteristics – High-Speed SD Mode NO. PARAMETER 1.15 V 1.0 V UNIT MIN MAX MIN MAX High-Speed SD Mode 1/HSSD 1/tc(clk) Frequency(1), mmcx_ clk (2) 48 24 ns 1 HSSD2 tW(clkH) Typical pulse duration, output clk high X(3)*PO(4) X(3)*PO(4) ns (1) Related with the output clk maximum and minimum frequencies programmable in I/F module. (2) In mmcx_clk, 'x' is equal to 1, 2, or 3. (3) The X parameter is defined as shown in Table 6-135. (4) PO = output clk period in ns. 244 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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