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OMAP3530ECUS72 数据表(PDF) 156 Page - Texas Instruments |
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OMAP3530ECUS72 数据表(HTML) 156 Page - Texas Instruments |
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156 / 265 page  OMAP3530, OMAP3525 SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 www.ti.com 6.4 External Memory Interfaces The OMAP3530/25 processor includes the following external memory interfaces: • General-purpose memory controller (GPMC) • SDRAM controller (SDRC) 6.4.1 General-Purpose Memory Controller (GPMC) The GPMC is the OMAP3530/25 unified memory controller used to interface external memory devices such as: • Asynchronous SRAM-like memories and ASIC devices • Asynchronous page mode and synchronous burst NOR flash • NAND flash 6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing Table 6-3 and Table 6-4 assume testing over the recommended operating conditions (see Figure 6-2 through Figure 6-5) and electrical characteristic conditions. Table 6-2. GPMC/NOR Flash Synchronous Mode Timing Conditions TIMING CONDITION PARAMETER VALUE UNIT Input Conditions tR Input signal rise time 1.8 ns tF Input signal fall time 1.8 ns Output Conditions CLOAD Output load capacitance 15.94 pF Table 6-3. GPMC/NOR Flash Interface Timing Requirements – Synchronous Mode(1) NO. PARAMETER OPP3 OPP2 OPP1(2) UNIT MIN MAX MIN MAX MIN MAX F12 tsu(DV-CLKH) Setup time, read gpmc_d[15:0] 1.9 1.9 3.2 ns valid before gpmc_clk high F13 th(CLKH-DV) Hold time, read gpmc_d[15:0] 1.9 1.9 1.9 ns valid after gpmc_clk high F21 tsu(WAITV-CLKH) Setup time, gpmc_waitx(3) valid 1.9 1.9 3.2 ns before gpmc_clk high F22 th(CLKH-WAITV) Hold Time, gpmc_waitx(3) valid 2.5 2.5 2.5 ns after gpmc_clk high (1) For VDD2 (vdd_core) OPP voltages, see Section 3.3, Recommended Operating Conditions. (2) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1. (3) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see the OMAP35x Technical Reference Manual (literature number SPRUF988). Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode NO. PARAMETER 1.15 V 1.0 V 0.9 V UNIT MIN MAX MIN MAX MIN MAX F0 tc(CLK) Cycle time(15), output 10 12.05 25 ns clock gpmc_clk period F1 tw(CLKH) Typical pulse duration, 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) ns output clock gpmc_clk high F1 tw(CLKL) Typical pulse duration, 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) 0.5 P(12) ns output clock gpmc_clk low tdc(CLK) Duty cycle error, output –500 500 –602 602 –1250 1250 ps clk gpmc_clk 156 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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