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OMAP3530ECUS72 数据表(PDF) 97 Page - Texas Instruments |
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OMAP3530ECUS72 数据表(HTML) 97 Page - Texas Instruments |
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97 / 265 page  OMAP3530, OMAP3525 www.ti.com SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 Table 2-6. External Memory Interfaces – SDRC Signals Description (continued) SIGNAL DESCRIPTION TYPE(1) BALL BALL TOP BALL BOTTOM BALL TOP BALL BOTTOM NAME BOTTOM (CBB Pkg.) (CBC Pkg.) (CBC Pkg.) (CUS Pkg.) (CBB Pkg.) sdrc_d27 SDRAM data bit 27 IO B20 D23 NA C20 B16 sdrc_d28 SDRAM data bit 28 IO D20 E22 NA D21 C16 sdrc_d29 SDRAM data bit 29 IO A21 E23 NA E20 D16 sdrc_d30 SDRAM data bit 30 IO B21 G22 NA E21 B17 sdrc_d31 SDRAM data bit 31 IO C21 G23 NA G21 B18 sdrc_ba0 SDRAM bank select 0 O H9 AB21 NA AA18 C18 sdrc_ba1 SDRAM bank select 1 O H10 AC21 NA V20 D18 sdrc_a0 SDRAM address bit 0 O A4 N22 NA G20 A4 sdrc_a1 SDRAM address bit 1 O B4 N23 NA K20 B4 sdrc_a2 SDRAM address bit 2 O B3 P22 NA J20 D6 sdrc_a3 SDRAM address bit 3 O C5 P23 NA J21 B3 sdrc_a4 SDRAM address bit 4 O C4 R22 NA U21 B2 sdrc_a5 SDRAM address bit 5 O D5 R23 NA R20 C3 sdrc_a6 SDRAM address bit 6 O C3 T22 NA M21 E3 sdrc_a7 SDRAM address bit 7 O C2 T23 NA M20 F6 sdrc_a8 SDRAM address bit 8 O C1 U22 NA N20 E10 sdrc_a9 SDRAM address bit 9 O D4 U23 NA K21 E9 sdrc_a10 SDRAM address bit 10 O D3 V22 NA Y16 E7 sdrc_a11 SDRAM address bit 11 O D2 V23 NA N21 G6 sdrc_a12 SDRAM address bit 12 O D1 W22 NA R21 G7 sdrc_a13 SDRAM address bit 13 O E2 W23 NA AA15 F7 sdrc_a14 SDRAM address bit 14 O E1 Y22 NA Y12 F9 sdrc_ncs0 Chip select 0 O H11 M22 NA T21 A19 sdrc_ncs1 Chip select 1 O H12 M23 NA T20 B19 sdrc_clk Clock IO A13 A11 NA A12 A10 sdrc_nclk Clock Invert O A14 B11 NA B13 A11 sdrc_cke0 Clock Enable 0 O H16 J22 NA Y15 B20 sdrc_cke1 Clock Enable 1 O H17 J23 NA Y13 C20 sdrc_nras SDRAM Row Access O H14 L23 NA V21 D19 sdrc_ncas SDRAM column O H13 L22 NA U20 C19 address strobe sdrc_nwe SDRAM write enable O H15 K23 NA Y18 A20 sdrc_dm0 Data Mask 0 O B7 C1 NA H1 B6 sdrc_dm1 Data Mask 1 O A16 A17 NA A14 B13 sdrc_dm2 Data Mask 2 O B11 A6 NA A4 A7 sdrc_dm3 Data Mask 3 O C20 A20 NA A18 A16 sdrc_dqs0 Data Strobe 0 IO A6 C2 NA C2 A5 sdrc_dqs1 Data Strobe 1 IO A17 B17 NA B15 A13 sdrc_dqs2 Data Strobe 2 IO A10 B6 NA B8 A8 sdrc_dqs3 Data Strobe 3 IO A20 B20 NA A19 A17 Copyright © 2008–2013, Texas Instruments Incorporated TERMINAL DESCRIPTION 97 Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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