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OMAP3530ECUS72 数据表(PDF) 102 Page - Texas Instruments |
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OMAP3530ECUS72 数据表(HTML) 102 Page - Texas Instruments |
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102 / 265 page  OMAP3530, OMAP3525 SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 www.ti.com Table 2-14. Serial Communication Interfaces – McBSP LP Signals Description (continued) SIGNAL NAME DESCRIPTION TYPE(1) BALL BOTTOM BALL BOTTOM BALL BOTTOM (CBB Pkg.) (CBC Pkg.) (CUS Pkg.) mcbsp2_dr Received serial data I R21 T18 V19 mcbsp2_dx Transmitted serial data IO M21 R19 R20 mcbsp2_clkx Combined serial clock IO N21 R18 T21 mcbsp2_fsx Combined frame synchronization IO P21 U18 V20 MULTICHANNEL SERIAL (McBSP LP 3) mcbsp3_dr Received serial data I AE6 / AB25 / U21 T20 / AA24 / N3 V5 / Y18 mcbsp3_dx Transmitted serial data IO AF6 / AB26 / V21 U17 / Y24 / P3 V6 / W18 mcbsp3_clkx Combined serial clock IO AF5 / AA25 / W21 T17 / AD22 / U3 W4 / V18 mcbsp3_fsx Combined frame synchronization IO AE5 / AD25 / K26 P20 / AD21 / W3 V4 / AA19 MULTICHANNEL SERIAL (McBSP LP 4) mcbsp4_dr Received serial data I R8 / AD1 C4 / U4 G5 mcbsp4_dx Transmitted serial data IO P8 / AD2 B5 / R3 F3 mcbsp4_clkx Combined serial clock IO T8 / AE1 B4 / V3 F4 mcbsp4_fsx Combined frame synchronization IO N8 / AC1 C5 / T3 G4 MULTICHANNEL SERIAL (McBSP LP 5) mcbsp5_dr Received serial data I AE11 Y3 AC5 mcbsp5_dx Transmitted serial data IO AF13 AE3 AC8 mcbsp5_clkx Combined serial clock IO AF10 AB2 AC1 mcbsp5_fsx Combined frame synchronization IO AH9 AB1 AD2 Table 2-15. Serial Communication Interfaces – McSPI Signals Description SIGNAL NAME DESCRIPTION TYPE(1) BALL BOTTOM BALL BOTTOM BALL BOTTOM (CBB Pkg.) (CBC Pkg.) (CUS Pkg.) MULTICHANNEL SERIAL PORT INTERFACE (McSPI1) mcspi1_clk SPI Clock IO AB3 P9 T5 mcspi1_simo Slave data in, master data out IO AB4 P8 R4 mcspi1_somi Slave data out, master data in IO AA4 P7 T4 mcspi1_cs0 SPI Enable 0, polarity configured by IO AC2 R7 T6 software mcspi1_cs1 SPI Enable 1, polarity configured by O AC3 R8 NA software mcspi1_cs2 SPI Enable 2, polarity configured by O AB1 R9 NA software mcspi1_cs3 SPI Enable 3, polarity configured by O AB2 T8 R5 software MULTICHANNEL SERIAL PORT INTERFACE (McSPI2) mcspi2_clk SPI Clock IO AA3 W7 N5 mcspi2_simo Slave data in, master data out IO Y2 W8 N4 mcspi2_somi Slave data out, master data in IO Y3 U8 N3 mcspi2_cs0 SPI Enable 0, polarity configured by IO Y4 V8 M5 software mcspi2_cs1 SPI Enable 1, polarity configured by O V3 V9 M4 software MULTICHANNEL SERIAL PORT INTERFACE (McSPI3) mcspi3_clk SPI Clock IO H26 / AE2 / AE13 W10 / M24 / AA3 G24 / Y1 / AD8 mcspi3_simo Slave data in, master data out IO H25 / AG5 / AF11 R10 / M26 / AC3 H23 / AB5 / AD6 mcspi3_somi Slave data out, master data in IO E28 / AH5 / AG12 F25 / T10 / AD4 D23 / AB3 / AC6 mcspi3_cs0 SPI Enable 0, polarity configured by IO J26 / AF4 / AH12 U9 / N24 / AD3 K22 / V3 / AC7 software mcspi3_cs1 SPI Enable 1, polarity configured by O AC27 / AG4 / AH14 AC25 / U10 / AD2 V21 / W3 / AD9 software MULTICHANNEL SERIAL PORT INTERFACE (McSPI4) (1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog) 102 TERMINAL DESCRIPTION Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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