PL123E-09SI-R datasheet(6/10 Pages) MICREL

6 / 10 page

(Preliminary)

PL123E-09

Low Skew Zero Delay Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 6

3.3V AND 2.5V AC ELECTRICAL SPECIFICATIONS

Description

Parameter Test Conditions

Min

Typ

Max

Unit

Maximum Frequency[7]

(Input/Output)

1/t1

3.3V High Drive

–

220

MHz

3.3V Standard Drive

–

167

MHz

2.5V High Drive

–

200

MHz

2.5V Standard Drive

–

134

MHz

Input Duty Cycle

(PLL Mode only)

TIDC

<133.3 MHz

–

>133.3 MHz

–

Output Duty Cycle[8]

t2 ÷ t1

<133.3 MHz

–

>133.3 MHz

–

Rise, Fall Time (3.3V)[8]

t3,t4

Standard Drive, CL = 30 pF, <100 MHz

–

1.6

–

Standard Drive, CL = 22 pF, <133.3 MHz

–

1.6

–

Standard Drive, CL = 15 pF, <167 MHz

–

0.6

–

High Drive, CL = 30 pF, <100 MHz

–

1.2

–

High Drive, CL = 22 pF, <133.3 MHz

–

1.2

–

High Drive, CL = 15 pF, >133.3 MHz

–

0.5

–

Rise, Fall Time (2.5V)[8]

t3, t4

Standard Drive, CL = 15 pF, <133.33 MHz

–

1.5

–

High Drive, CL = 30 pF, <100 MHz

–

2.1

–

High Drive, CL = 22 pF, <133.3 MHz

–

1.3

–

High Drive, CL = 15 pF, >133.3 MHz

–

1.2

–

Output to Output Skew [8]

All outputs equally loaded

–

100

Delay, REF Rising Edge

to CLKOUT Rising Edge[8]

PLL enabled @ 3.3V

–100

–

100

PLL enabled @2.5V

–200

–

200

Part to Part Skew[8]

Measured at VDD/2.

Any output to any output, 3.3V supply

–

±150

Measured at VDD/2.

Any output to any output, 2.5V supply

–

±300

PLL Lock Time[8]

tLOCK

Stable power supply, valid clocks pre-

sented on REF and CLKOUT pins

–

1.0

Cycle-to-Cycle Jitter,

Peak[8, 9]

TJCC

3.3V, >66 MHz, <15 pF

–

3.3V, >66 MHz, <30 pF, Standard. Drive

–

125

3.3V, >66 MHz, <30 pF, High Drive

–

100

2.5V, >66 MHz, <15 pF, Standard. Drive

–

2.5V, >66 MHz, <15 pF, High Drive

–

2.5V, >66 MHz, <30 pF, High Drive

–

145

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