(Preliminary)

PL123E-09

Low Skew Zero Delay Buffer

LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a pe rformance optimized PCB design:

Signal Integrity and Termination

Considerations

- Keep traces short!

- Trace = Inductor. With a capacitive load this equals

ringing!

- Long trace = Transmission Line. Without proper termi-

nation this will cause reflections ( looks like ringing ).

- Design long traces as “striplines” or “microstrips” with

defined impedance.

- Match trace at one side to avoid reflections bouncing

back and forth.

Decoupling and Power Supply

Considerations

- Place decoupling capacitors as close as possible to

the VDD pin(s) to limit noise from the power supply

- Addition of a ferrite bead in series with VDD can

help prevent noise from other board sources

- Value of decoupling capacitor is frequency depend-

ant. Typical values to use are 0.1

F for designs

using frequencies < 50MHz and 0.01

F for designs

using frequencies > 50MHz.

Typical CMOS termination

Place Series Resistor as close as possible to CMOS output

CMOS Output Buffer

( Typical buffer impedance 20



To CMOS Input

50

 line

resistor at each of the output

clocks to enhance the

stability of the output signal