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ADP1761ACPZ-R7 数据表(PDF) 5 Page - Analog Devices

部件名 ADP1761ACPZ-R7
功能描述  CMOS Linear Regulator
PDF  19 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP1761ACPZ-R7 数据表(HTML) 5 Page - Analog Devices

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ADP1761
Data Sheet
Rev. 0 | Page 4 of 18
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
THERMAL SHUTDOWN
Threshold
TSSD
TJ rising
150
°C
Hysteresis
TSSD-HYS
15
°C
POWER-GOOD (PG) OUTPUT THRESHOLD
Output Voltage
Falling
PGFALL
1.1 V ≤ VIN ≤ 1.98 V
−7.5
%
Rising
PGRISE
1.1 V ≤ VIN ≤ 1.98 V
−5
%
PG OUTPUT
Output Voltage Low
PGLOW
1.1 V ≤ VIN ≤ 1.98 V, IPG ≤ 1 mA
0.35
V
Leakage Current
IPG-LKG
1.1 V ≤ VIN ≤ 1.98 V
0.01
1
μA
Delay1
PGDELAY
ENRISING to PGRISING
0.75
ms
PRECISION EN INPUT
1.1 V ≤ VIN ≤ 1.98 V
Logic Input
High
ENHIGH
595
625
690
mV
Low
ENLOW
550
580
630
mV
Input Logic Hysteresis
ENHYS
45
mV
Input Leakage Current
IEN-LKG
EN = VIN or GND
0.01
1
μA
Input Delay Time
tIEN-DLY
From EN rising from 0 V to VIN to 0.1 × VOUT
100
μs
UNDERVOLTAGE LOCKOUT
UVLO
Input Voltage
Rising
UVLORISE
TJ = −40°C to +125°C
1.01
1.06
V
Falling
UVLOFALL
TJ = −40°C to +125°C
0.87
0.93
V
Hysteresis
UVLOHYS
90
mV
1 Guaranteed by design and characterization; not production tested.
2 Based on an endpoint calculation using 10 mA and 1 A loads.
3 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage, which applies only for output
voltages above 1.1 V.
4 Start-up time is defined as the time from the rising edge of EN to VOUT being at 90% of its nominal value.
5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
CAPACITANCE1
TA = −40°C to +125°C
Input
CIN
7.0
10
μF
Output
COUT
7.0
10
μF
Regulator
CREG
0.7
1
μF
Reference
CREF
0.7
1
μF
CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR)
RESR
TA = −40°C to +125°C
CIN, COUT
0.001
0.5
Ω
CREG, CREF
0.001
0.2
Ω
1 The minimum input and output capacitance must be >7.0 μF over the full range of the operating conditions. Consider the full range of the operating conditions in the
application during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and Z5U
capacitors are not recommended for use with any LDO.



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