 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
CS8412 数据表(PDF) 13 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS8412 数据表(HTML) 13 Page - Cirrus Logic |
|
|
13 / 38 page  CS8411 CS8412 DS61F1 13 data can be read twice or missed if the device con- trolling FSYNC and SCK is on a different time- base than the CS8411. If the audio data is read twice or missed, the SLIP bit in SR1 is set. SCED selects the SCK edge to output data on. SCED high causes data to be output on the falling edge, and SCED low causes data to be output on the rising edge. Audio Serial Port The audio serial port outputs the audio data portion from the received data and consists of three pins: SCK, SDATA, and FSYNC. SCK clocks the data out on the SDATA line. The edge that SCK uses to output data is programmable from CR2. FSYNC delineates the audio samples and may indicate the particular channel, left or right. Figure 10 illus- trates the multitude of formats that SDATA and FSYNC can take. Normal Modes SCK and FSYNC can be inputs (MSTR = 0) or out- puts (MSTR = 1), and are usually programmed as outputs. As outputs, SCK contains 32 periods for 24 Bits, Incl. Aux 16 Clocks 16 Clocks 16 Clocks 16 Clocks 32 Clocks 32 Clocks 32 Clocks 32 Clocks 00 01 10 11 1 1 1 1 FSYNC Output FSYNC Output FSYNC Output FSYNC Output FSF 00 01 10 11 MSTR 0 0 0 0 FSYNC Input FSYNC Input FSYNC Input FSYNC Input 10 (bit) 000 MSB First - 32 001 011 101 111 MSB Last LSB Last - 16 LSB Last - 18 LSB Last - 20 210 (bit) Name SDF 20 Bits LSB MSB LSB MSB LSB LSB LSB MSB LSB MSB LSB LSB MSB LSB MSB MSB LSB MSB LSB MSB 16 Bits 18 Bits 20 Bits 18 Bits 16 Bits MSB LSB MSB LSB MSB Left Sample Right Sample 32 Bits 32 Bits SPECIAL MODES: * Error flags are not accurate in these modes MSB LSB MSB LSB MSB 16 Bits 16 Bits MSB MSB MSB LSB LSB MSB MSB MSB LSB LSB Bi-Phase Mark Data Bi-Phase Mark Data 32 Bits 32 Bits LSB VUCP MSB AUX LSB AUX VUCP MSB AUX 210 MSTR Name SDF 110 0 MSB First - 24 010 0 MSB First - 16 010* 1 NRZ Data 100* 1 Bi-Phase Data 100 Async SCK 0 24 Bits, Incl. Aux 24 Bits, Incl. Aux 24 Bits, Incl. Aux 24 Bits, Incl. Aux 24 Bits, Incl. Aux 24 Bits, Incl. Aux 24 Bits, Incl. Aux Figure 10. CS8411 Serial Port SDATA and FSYNC Timing |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
