CAT5259

http://onsemi.com

6

Symbol

Parameter

Max

Units

Write Cycle Time

5

ms

Table 11. RELIABILITY CHARACTERISTICS

Symbol

Parameter

Reference Test Method

Min

Max

Units

Endurance

MIL−STD−883, Test Method 1033

1,000,000

Cycles/Byte

Data Retention

MIL−STD−883, Test Method 1008

100

Years

ESD Susceptibility

MIL−STD−883, Test Method 3015

2000

V

Latch-up

JEDEC Standard 17

100

mA

10.The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write

cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

11. This parameter is tested initially and after a design or process change that affects the parameter.

Figure 2. Bus Timing

SCL

SDA IN

SDA OUT

SERIAL BUS PROTOCOL

1. Data transfer may be initiated only when the bus is

not busy.

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock is high

will be interpreted as a START or STOP condition.

The device controlling the transfer is a master, typically a

processor or controller, and the device being controlled is the

slave. The master will always initiate data transfers and

provide the clock for both transmit and receive operations.

Therefore, the CAT5259 will be considered a slave device

in all applications.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of SDA

when SCL is HIGH. The CAT5259 monitors the SDA and

SCL lines and will not respond until this condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a

START condition. The Master then sends the address of the

particular slave device it is requesting. The four most

significant bits of the 8-bit slave address are fixed as 0101

for the CAT5259 (see Figure 6). The next four significant

bits (A3, A2, A1, A0) are the device address bits and define

which device the Master is accessing. Up to sixteen devices

may be individually addressed by the system. Typically,

+5 V and ground are hard-wired to these pins to establish the

device’s address.

After the Master sends a START condition and the slave

address byte, the CAT5259 monitors the bus and responds

with an acknowledge (on the SDA line) when its address

matches the transmitted slave address.