CAT5259

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8

Figure 5. Acknowledge Condition

ACKNOWLEDGE

1

START

SCL FROM

MASTER

89

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 6. Slave Address Bits

* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.

** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.

A0

A1

A2

A3

1

0

1

0

CAT5259

INSTRUCTION AND REGISTER DESCRIPTION

Slave Address Byte

The first byte sent to the CAT5259 from the

master/processor is called the Slave Address Byte. The most

significant four bits of the slave address are a device type

identifier. These bits for the CAT5259 are fixed at 0101[B]

(refer to Figure 8).

The next four bits, A3 − A0, are the internal slave address

and must match the physical device address which is defined

by the state of the A3 − A0 input pins for the CAT5259 to

successfully continue the command sequence. Only the

device which slave address matches the incoming device

address sent by the master executes the instruction. The A3

− A0 inputs can be actively driven by CMOS input signals

Instruction Byte

The next byte sent to the CAT5259 contains the

instruction and register pointer information. The four most

significant bits used provide the instruction opcode I3 − I0.

The R1 and R0 bits point to one of the four data registers of

each associated potentiometer. The least two significant bits

point to one of four Wiper Control Registers. The format is

shown in Figure 9.

Table 12. DATA REGISTER SELECTION

Data Register Selected

R1

R0

DR0

0

0

DR1

0

1

DR2

1

0

DR3

1

1

Figure 7. Write Timing

S

DR1 WCRDATA

S

T

O

P

P

BUS ACTIVITY:

MASTER

SDA LINE

S

T

A

R

T

SLAVE

ADDRESS

INSTRUCTION

BYTE

Fixed Variable

Figure 8. Identification Byte Format

ID3

ID2

ID1

ID0

A3

A2

A1

A0

01

01

(MSB)

(LSB)

Device Type Identifier

Slave Address

ACK

ACK

ACK