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MCP19035-AAAAE/MF 数据表(PDF) 23 Page - Microchip Technology |
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MCP19035-AAAAE/MF 数据表(HTML) 23 Page - Microchip Technology |
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23 / 44 page ![]() 2012-2013 Microchip Technology Inc. DS22326B-page 23 MCP19035 5.2.8 FEEDBACK LOOP COMPENSATION Since the MCP19035 implements a Voltage-Mode PWM control, a Type-III compensation network is recommended. Correct placing of poles and zeros require analysis of the Bode plots for the buck converter power train. FIGURE 5-1: Bode Plots for Buck Converter Power Train (Representation Using Asymptotes). The power train of a buck converter that uses voltage mode control is a second order system. At the LC resonance frequency, a double pole occurs; this pole will “push” the gain down with a slope of -40db/decade. This double pole also introduces a phase lag of -180°. The compensation network must counteract the effects of this double pole in order to achieve the stability of the system. The Equivalent Series Resistance (ESR) of the output capacitor introduces a zero that “pushes” the gain and phase up again. This zero helps the stability of the system if it occurs before the phase reaches the critical point of -180°. However, due to the performance criteria (output voltage ripple, efficiency), the application requires the use of low ESR capacitors. For capacitors that have very low ESR (ceramic capacitors), this zero occurs at high frequency, where the phase reaches the critical point. The frequencies for pole and zero are determined using Equation 5-20: EQUATION 5-20: POLE AND ZERO FREQUENCIES EQUATION 5-21: PWM MODULATOR GAIN The Type-III compensation network is represented in Figure 5-2: FIGURE 5-2: Type-III Compensation Network. Magnitude (dB) Frequency (log scale) AMOD 0dB -40 dB/decade -20 db/decade fLC fESR Phase (deg) 0° -90° -180° Frequency (log scale) f LC 1 2 LC OUT ------------------------------------- = f ESR 1 2 ESR C OUT ----------------------------------------------- = A MOD 20 V IN V RAMP --------------------- log 20 V IN log == Gs R 1 R 3 + R 1 R 3 C 1 --------------------------------- s 1 R 4 C 2 -------------------- + s 1 R 1 R 3 C 1 -------------------------------------- + ss C 2 C 3 + R 4 C 2 C 3 --------------------------------- + s 1 R 3 C 1 -------------------- + --------------------------------------------------------------------------------------------------- = Where: C1 R3 C3 R1 R2 C2 VREF R4 + - EA VIN COMP |
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