SC16C652 datasheet(21/41 Pages) PHILIPS

21 / 41 page

Philips Semiconductors

SC16C652

Dual UART with 32 bytes of transmit and receive FIFOs

Product data

Rev. 04 — 20 June 2003

21 of 41

9397 750 11634

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by

writing the appropriate bits in this register.

Table 16:

Line Control Register bits description

Bit

Symbol

Description

LCR[7]

Divisor latch enable. The internal baud rate counter latch and

Enhance Feature mode enable.

Logic 0 = Divisor latch disabled (normal default condition).

Logic 1 = Divisor latch enabled.

LCR[6]

Set break. When enabled, the Break control bit causes a break

condition to be transmitted (the TX output is forced to a logic 0

state). This condition exists until disabled by setting LCR[6] to a

logic 0.

Logic 0 = no TX break condition (normal default condition)

Logic1=forces the transmitter output (TX) to a logic 0 for

alerting the remote receiver to a line break condition.

5-3

LCR[5-3]

Programs the parity conditions (see Table 17).

LCR[2]

Stop bits. The length of stop bit is speciﬁed by this bit in

conjunction with the programmed word length (see Table 18).

Logic 0 or cleared = default condition.

1-0

LCR[1-0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 19).

Logic 0 or cleared = default condition.

Table 17:

LCR[5-3] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

no parity

ODD parity

EVEN parity

001forced parity ‘1’

111forced parity ‘0’

Table 18:

LCR[2] stop bit length

LCR[2]

Word length

Stop bit length (bit times)

5, 6, 7, 8

1-1

⁄2

6, 7, 8

Table 19:

LCR[1-0] word length

LCR[1]

LCR[0]

Word length

005

016

107

118

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