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STw5094

PCM Interface Timing

Note:

A signal is valid if it is above VIH or below VIL and invalid if it is between VIL and VIH.For the purpose of this specification the

following conditions apply (see Fig. 8):

a) All input signal are defined as: VIL = 0.2VCCIO, VIH = 0.8VCCIO, tR < 10ns, tF < 10ns.

b) Delay times are measured from the inputs signal valid to the output signal valid.

c) Setup times are measured from the data input valid to the clock input invalid.

d) Hold times are measured from the clock signal valid to the data input invalid.

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Hold Time MCLK low to FS low

10

ns

Setup Time, FS high to MCLK low

30

ns

Delay Time, MCLK high to data

valid

Load = 20pF

100

ns

Delay Time, MCLK low to

DX disabled

10

100

ns

Delay Time, FS high to data valid

Load = 20pF; Applies only if FS

rises later than MCLK rising edge

in Non Delayed Mode only

100

ns

Setup Time, DR valid to MCLK

receive edge

20

ns

Hold Time, MCLK low to DR

invalid

10

ns

Hold Time MCLK High to FS low

30

ns

Setup Time, FS high to MCLK

High

30

ns

Delay Time, MCLK low to data

valid

Load = 20pF

100

ns

Delay Time, MCLK High to DX

disabled

10

100

ns

Hold Time, MCLK High to DR

invalid

20

ns

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Clock Frequency

400

kHz

Clock High Time

600

ns

Clock Low Time

1300

ns

SDA and SCL Rise Time

1000

ns

SDA and SCL Fall Time

300

ns

Start Condition Hold Time

600

ns

Start Condition Setup Time

600

ns

Data Input Hold Time

0

ns

Data Input Setup Time

250

ns

Stop Condition Setup Time

600

ns

Bus Free Time

1300

ns