12

06/19/2000

GL600USB/GL600USB-A/GL600USB-B

Revision 1.3

17h

FFDAT0

Endpoint 0 FIFO port

18h

FFDAT1

Endpoint 1 FIFO port

19h

EP0RXST

Endpoint 0 receiving status register

Table 4 -1 USB Function Register Summary

DEVCTL (Address 10h, Device control register)

R/W

[1]

R/W

R/W

R/W

R/W

R/W

TXSE0

EP0STL

EP1STL

WAKE

WKDIS

PWRDN

TXSE0: Set and clear transmitting SE0 bit

1: Set transmitting SE0

0: Clear transmitting SE0

EP0STL: Endpoint 0 stall bit. This bit will be cleared automatically by hardware when SETUP packet is

received

1: Endpoint 0 will respond with a STALL to a valid transaction except SETUP

0: Endpoint 0 will not respond with a STALL to a valid transaction

EP1STL: Endpoint 1 stall bit

1: Endpoint 1 will respond with a STALL to a valid IN transaction

0: Endpoint 1 will not respond with a STALL to a valid IN transaction

WAKE: Wake-up bit

1: Set this bit to wake up host controller by placing USB bus into K state

0: Clear this bit to force USB bus leave K state

WKDIS: Wake-up disable bit. The WAKE bit has no effect if WKDIS bit is set to 1.

1: Disable remote wake-up capability

0: Enable remote wake-up capability

PWRDN: Power-down mode bit. Writing 1 to this bit will enter power-down mode

If USB suspend is detected, firmware can set this bit to enter power-down mode. In power-down

mode, crystal/resonator will stop. The PWRDN bit will be cleared automatically by hardware and

crystal/resonator will restart when the internal RC timer timeout (about 500ms). Firmware should

check buttons and photo position encoders of the mouse. If mouse status is not changed, Firmware

should set the PWRDN bit to enter power down mode again. Power consumption in suspend mode

depends on how much time the firmware checking mouse status changed. Hardware will also clear

PWRDN bit automatically when USB D+ or D- is toggled.

0: Normal mode, not power-down

Value on POR: “1 - 0 - 0 0 0 0”

[2]

Note 1: “R/W” means readable and writable bit. All reserved fields should not be changed by firmware.

Note 2: “-“ means unimplemented read as 0

EVTFLG (Address 12h, Event flag register)

R/W1C

[1]

R/W1C

R/W1C

R/W1C

R/W1C

RESUME

SUSPD

EP1TX

EP0TX

EP0RX

RESUME: Global resume bit

1: Global resume (USB D+/D- toggle) was detected

0: Global resume was not detected

SUSPD: Global suspend bit

1: Global suspend (USB idle more than 3ms) was detected

0: Global suspend was not detected

EP1TX: Endpoint 1 transmitting status bit

1: Data has been sent from endpoint 1

0: Data has not been sent from endpoint 1

EP0TX: Endpoint 0 transmitting status bit

1: Data has been sent from endpoint 0

0: Data has not been sent from endpoint 0

EP0RX: Endpoint 0 receiving status bit