15

06/19/2000

GL600USB/GL600USB-A/GL600USB-B

Revision 1.3

82h

PCL

Program Counter’s low byte

83h

STATUS

Status register

84h

INDAR

Indirect address register

86h

PORT1CON

Port 1 direction control register

87h

PORT2CON

Port 2 direction control register

8Ah

PCHBUF

Write buffer of Program Counter’s bit 10-8

8Bh

INTEN

Interrupt enable register

Table 4 -2 MCU Function Register Summary

INDR (Address 00h/80h)

INDR is not a physical register. Addressing INDR register will cause indirect addressing. Any instruction

using the INDF register actually accesses the register pointed by the INDAR register. The indirect

addressing method only can be used for general purpose registers.

TIMER (Address 01h, Timer register)

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

TIMER7

TIMER6

TIMER5

TIMER4

TIMER3

TIMER2

TIMER1

TIMER0

The timer starts to count up after power on reset. The TMROF bit at INTEN register will be set when the

TIMER register overflows from FFh to 00h. If both TMROEN and GIE bits at INTEN register are set, an

interrupt will be generated when TIMER register overflows.

Value on POR: “0 0 0 0 0 0 0 0”

PCL (Address 02h/82h, Program Counter’s low byte)

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

PCL7

PCL6

PCL5

PCL4

PCL3

PCL2

PCL1

PCL0

The Program Counter (PC) is 11-bits wide. The low byte comes from the PCL register, which is a readable

and writable register. The high byte is not directly readable or writable and comes from PCHBUF. The

GL600USB has a 4 level deep x 11-bits wide hardware stake. The stake space is not part of either program

or data space and the stack pointer is not readable or writable. The PC is pushed onto the stack when a

CALL instruction is executed or an interrupt causes a branch. The stack is poped in the event of a RETIA,

RETI or a RET instruction execution. PCHBUF is not affected by a push or pop operation.

When write to PCL command executed, all 3 bits of PCHBUF will be loaded to PC because PCL is only a

8 bits register.

Value on POR: “0 0 0 0 0 0 0 0”

Status (Address 03h, Status register)

R/W

R/W

R/W

R/W

BS

ZO

HC

CA

BS: Bank Select. Because only 7 bits (bit 0~bit 6) operand implied by instruction for register address, this

bit is used as address bit 7 when register access.

1: Bank 1 (80h-FFh)

0: Bank 0 (00h-7Fh)

ZO: Zero bit

1: The result of an arithmetic or logic operation is zero

0: The result of an arithmetic or logic operation is not zero

HC: Half Carry/Borrow bit

1: Carry or not borrow from the 4

0: Borrow or not carry from the 4

CA: Carry/Borrow bit

1: Carry or not borrow from the most significant bit

0: Borrow or not carry from the most significant bit