6

CAT93C56/57

Doc. No. 1088, Rev. M

Erase

Upon receiving an ERASE command and address, the

CS (Chip Select) pin must be deasserted for a minimum

clear cycle of the selected memory location. The clocking

of the SK pin is not necessary after the device has

entered the self clocking mode. The ready/busy status of

the CAT93C56/57 can be determined by selecting the

device and polling the DO pin. Once cleared, the content

of a cleared location returns to a logical “1” state.

Erase/Write Enable and Disable

The CAT93C56/57 powers up in the write disable state.

Any writing after power-up or after an EWDS (write

disable) instruction must first be preceded by the EWEN

(write enable) instruction. Once the write instruction is

enabled, it will remain enabled until power to the device

is removed, or the EWDS instruction is sent. The EWDS

instruction can be used to disable all CAT93C56/57

write and clear instructions, and will prevent any

accidental writing or clearing of the device. Data can be

read normally from the device regardless of the write

enable/disable status.

Erase All

Upon receiving an ERAL command, the CS (Chip Select)

falling edge of CS will start the self clocking clear cycle

of all memory locations in the device. The clocking of the

SK pin is not necessary after the device has entered the

self clocking mode. The ready/busy status of the

CAT93C56/57 can be determined by selecting the device

and polling the DO pin. Once cleared, the contents of all

memory bits return to a logical “1” state.

Write All

Upon receiving a WRAL command and data, the CS

(Chip Select) pin must be deselected for a minimum of

data write to all memory locations in the device. The

clocking of the SK pin is not necessary after the device

has entered the self clocking mode. The ready/busy

status of the CAT93C56/57 can be determined by

selecting the device and polling the DO pin. It is not

necessary for all memory locations to be cleared before

the WRAL command is executed.

Figure 4. Erase Instruction Timing

SK

CS

DI

DO

STANDBY

HIGH-Z

HIGH-Z

1

AN

AN-1

BUSY

READY

STATUS VERIFY

tSV

tHZ

tEW

tCS

11

A0