Where R

the maximum load current. The zero created by the ESR of

the output capacitor is generally very high frequency if the

ESR is small. If low ESR capacitors are used it can be

neglected. If higher ESR capacitors are used see the High

Output Capacitor ESR Compensation section.

RIGHT HALF PLANE ZERO

A current mode control boost regulator has an inherent right

half plane zero (RHP zero). This zero has the effect of a zero

in the gain plot, causing an imposed +20dB/decade on the

rolloff, but has the effect of a pole in the phase, subtracting

another 90˚ in the phase plot. This can cause undesirable

effects if the control loop is influenced by this zero. To ensure

the RHP zero does not cause instability issues, the control

the frequency of the RHP zero. This zero occurs at a fre-

quency of:

where I

SELECTING THE COMPENSATION COMPONENTS

The first step in selecting the compensation components R

C

and C

loop. Simply choose values for R

given in the Introduction to Compensation section to set this

pole in the area of 10Hz to 500Hz. The frequency of the pole

created is determined by the equation:

where R

approximately 1M

Ω. Since R

R

can be neglected until a value is chosen to set the zero f

f

capacitor, f

ent load currents as shown by the equation, so setting the

zero is not exact. Determine the range of f

pected loads and then set the zero f

mately in the middle. The frequency of this zero is deter-

mined by:

Now R

Check to make sure that the pole f

500Hz range, change each value slightly if needed to ensure

both component values are in the recommended range. After

checking the design at the end of this section, these values

can be changed a little more to optimize performance if

desired. This is best done in the lab on a bench, checking the

load step response with different values until the ringing and

overshoot on the output voltage at the edge of the load steps

is minimal. This should produce a stable, high performance

circuit. For improved transient response, higher values of R

C

should be chosen. This will improve the overall bandwidth

which makes the regulator respond more quickly to tran-

sients. If more detail is required, or the most optimal perfor-

mance is desired, refer to a more in depth discussion of

compensating current mode DC/DC switching regulators.

HIGH OUTPUT CAPACITOR ESR COMPENSATION

When using an output capacitor with a high ESR value, or

just to improve the overall phase margin of the control loop,

another pole may be introduced to cancel the zero created

by the ESR. This is accomplished by adding another capaci-

tor, C

parallel with the series combination of R

should be placed at the same frequency as f

zero. The equation for this pole follows:

To ensure this equation is valid, and that C

without negatively impacting the effects of R

must be greater than 10f

CHECKING THE DESIGN

The final step is to check the design. This is to ensure a

This is done by calculating the open-loop DC gain, A

this value is known, you can calculate the crossover visually

by placing a −20dB/decade slope at each pole, and a

+20dB/decade slope for each zero. The point at which the

gain plot crosses unity gain, or 0dB, is the crossover fre-

zero, the phase margin should be high enough for stability.

The phase margin can also be improved by adding C

discussed earlier in the section. The equation for A

given below with additional equations required for the calcu-

lation:

mc ) 0.181fs (in V/s)

where R

mum input voltage, g

tance found in the Electrical Characteristics table, and R

D-

SON

is the value chosen from the graph "R

the Typical Performance Characteristics section.

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