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831742AGILF 数据表(PDF) 11 Page - Integrated Device Technology |
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831742AGILF 数据表(HTML) 11 Page - Integrated Device Technology |
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11 / 20 page ![]() 11 ©2016 Integrated Device Technology, Inc April 5, 2016 831742I Data Sheet Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. Figure 2A. CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 2C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2E. CLK/nCLK Input Driven by a 3.3V HCSL Driver Figure 2B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver R1 50 Ω R2 50 Ω 1.8V Zo = 50 Ω Zo = 50 Ω CLK nCLK 3.3V LVHSTL IDT LVHSTL Driver Differential Input |
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