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831752 数据表(PDF) 5 Page - Integrated Device Technology

部件名 831752
功能描述  Clock Switch for ATCA/AMC and PCIe Applications
PDF  18 Pages
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制造商  IDT [Integrated Device Technology]
网页  http://www.idt.com
标志 IDT - Integrated Device Technology

831752 数据表(HTML) 5 Page - Integrated Device Technology

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©2016 Integrated Device Technology, Inc
Revision B June 28, 2016
831752 Data Sheet
Table 5B. HCSL AC Characteristics, VDD = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
NOTE: Measurements taken with Q output and FCLK output.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All measurements were taken with FCLK, nFCLK and Q, nQ operating as outputs unless otherwise noted.
NOTE 1: Measured from the differential input cross point to the differential output crossing point.
NOTE 2: Measurement taken from differential waveform.
NOTE 3: Measurement from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 4: TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB ±100 differential range. See Parameter Measurement Information Section.
NOTE 5: Measurement taken from single-ended waveform.
NOTE 6: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.
See Parameter Measurement Information Section.
NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 10: Defined as the total variation of all crossing voltage of rising Q and falling nQ. This is the maximum allowed variance in the VCROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 11: Input duty cycle must be 50%.
NOTE 12: Matching applies to rising edge rate for Q and falling edge rate for nQ. It is measured using a ±75mV window centered on the
median crosspoint where Q meets nQ falling. The median crosspoint is used to calculate the voltage thresholds the oscilloscope is to use for
the edge rate calculations. The rise edge rate of Q should be compared to the fall edge rate of nQ, the maximum allowed difference should not
exceed 20% of the slowest edge rate.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
100
500
MHz
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Plot
100MHz, Integration Range:
12kHz – 20MHz
0.3
0.505
ps
tPD
Propagation Delay, NOTE 1
FCLK to Q
1.75
3.65
ns
CLK to Q
1.95
3.90
ns
CLK to FCLK
1.50
3.70
ns
MUXISOL
Mux Isolation
f = 100MHz
-70
dB
Edge Rate
Rise/Fall Edge Rate; NOTE 2, 3
0.6
4
V/ns
VRB
Ringback Voltage; NOTE 2, 4
-100
100
mV
tSTABLE
Time before VRB is allowed;
NOTE 2, 4
500
ps
VMAX
Absolute Max Output Voltage;
NOTE 5, 6
800
1350
mV
VMIN
Absolute Min Output Voltage;
NOTE 5, 7
-300
-35
mV
VCROSS
Absolute Crossing Voltage;
NOTE 5, 8, 9
250
385
650
mV
V
CROSS
Total Variation of VCROSS over all
edges; NOTE 5, 8, 10
40
140
mV
odc
Output Duty Cycle; NOTE 11
f
312.5MHz
44
50
56
%
f > 312.5MHz
40
50
60



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