LPS22HB datasheet(39/49 Pages) STMICROELECTRONICS

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LPS22HB

The BOOT bit is used to refresh the content of the internal registers stored in the Flash

memory block. At device power-up, the content of the Flash memory block is transferred to

the internal registers related to the trimming functions to allow correct behavior of the device

itself. If for any reason the content of the trimming registers is modified, it is sufficient to use

this bit to restore the correct values. When the BOOT bit is set to ‘1’, the content of the

internal Flash is copied into the corresponding internal registers and is used to calibrate the

device. These values are factory trimmed and they are different for every device. They allow

the correct behavior of the device and normally they should not be changed. At the end of

the boot process the BOOT bit is set again to ‘0’ by hardware. The BOOT bit takes effect

after one ODR clock cycle.

SWRESET is the software reset bit. The following device registers (INTERRUPT_CFG

(0Bh), THS_P_L (0Ch), REF_P_H (17h), CTRL_REG1 (10h), CTRL_REG2 (11h),

CTRL_REG3 (12h), FIFO_CTRL (14h), REF_P_XL (15h), REF_P_L (16h), REF_P_H

(17h)) are reset to the default value if the SWRESET bit is set to '1'. The SWRESET bit

returns to '0' by hardware.

The ONE_SHOT bit is used to start a new conversion when the ODR[2:0] bits in

CTRL_REG1 (10h) are set to ‘000’. Writing a ‘1’ in ONE_SHOT triggers a single

measurement of pressure and temperature. Once the measurement is done, the

ONE_SHOT bit will self-clear, the new data are available in the output registers, and the

STATUS (27h) bits are updated.

9.7

CTRL_REG3 (12h)

Control register 3 - INT_DRDY pin control register

76543210

INT_H_L

PP_OD

F_FSS5

F_FTH

F_OVR

DRDY

INT_S2

INT_S1

INT_H_L

Interrupt active-high/low. Default value: 0

(0: active high; 1: active low)

PP_OD

Push-pull/open drain selection on interrupt pads. Default value: 0

(0: push-pull; 1: open drain)

F_FSS5

FIFO full flag on INT_DRDY pin. Default value: 0

(0: disable; 1: enable)

F_FTH

FIFO watermark status on INT_DRDY pin. Default value: 0

(0: disable; 1: enable)

F_OVR

FIFO overrun interrupt on INT_DRDY pin. Default value: 0

(0: disable; 1: enable)

DRDY

Data-ready signal on INT_DRDY pin. Default value: 0

(0: disable; 1: enable)

INT_S[2:1]

Data signal on INT_DRDY pin control bits. Default value: 00

Refer to Table 19.

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