STM8AF5269 datasheet(38/125 Pages) STMICROELECTRONICS

38 / 125 page

Pinouts and pin description

STM8AF526x/8x/Ax STM8AF6269/8x/Ax

38/125

DocID14395 Rev 15

78 62 46

PD5/

LINUART_TX

I/O X XX

X Port D5

LINUART

data

transmit

79 63 47

PD6/

LINUART_RX

I/O X XX

X Port D6

LINUART

data

receive

80 64 48

PD7/TLI(5)

I/O X XX

X Port D7

Top level

interrupt

1. In Halt/Active-halt mode, this pin behaves as follows:

- The input/output path is disabled.

- If the HSE clock is used for wakeup, the internal weak pull-up is disabled.

- If the HSE clock is off, the internal weak pull-up setting is used. It is configured through Px_CR1[7:0] bits of the

corresponding port control register. Px_CR1[7:0] bits must be set correctly to ensure that the pin is not left floating in

Halt/Active-halt mode.

2. SPI and USTART are not available in STM8AF5286UC, refer to Figure 7: STM8AF52x6 VFQFPN32 32-pin pinout for the

pin names.

3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, week pull-up and protection diode to VDD are

not implemented)

4. The PD1 pin is in input pull-up during the reset phase and after reset release.

5. If this pin is configured as interrupt pin, it will trigger the TLI.

Table 11. STM8AF526x/8x/Ax and STM8AF6269/8x/Ax pin description (continued)

Pin number

Pin name

Input

Output

Main

function

(after

reset)

Default

alternate

function

Alternate

function

after remap

[option bit]

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