PL138-48

DS20005543B-page 6

 2016 Microchip Technology Inc.

2.0

PIN DESCRIPTIONS

FIGURE 2-1:

Pin Configuration, 16-Pin QFN.

FIGURE 2-2:

Pin Configuration, 20-Pin TSSOP.

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

Pin Number

QFN-16

Pin Number

TSSOP-20

Pin Name

Type

Description

41

P

Power supply pin connection.

16

2

CLK-EN

I

Synchronizing clock enable.

When HIGH, clock outputs follow clock input. When LOW, Q

outputs are forced low, QB outputs are forced high.

LVTTL/LVCMOS interface levels.

50 kΩ internal pull-up resistor.

—

3

CLK-SEL

I

Clock select input. When HIGH, selects CLK1 input. When

LOW, selects CLK0 input.

LVTTL/LVCMOS interface levels.

50 kΩ internal pull-down resistor.

2

4

CLK-IN0

I

True part of differential clock input signal. 75 kΩ internal

pull-down resistor.

3

5

CLK-IN0B

I

Complementary part of differential clock input signal.

100 kΩ internal pull-up and pull-down resistors.