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SST49LF080A 数据表(PDF) 21 Page - Microchip Technology |
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SST49LF080A 数据表(HTML) 21 Page - Microchip Technology |
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21 / 50 page  ©2014 Silicon Storage Technology, Inc. DS20005086B 11/14 21 8 Mbit LPC Flash SST49LF080A Data Sheet Figure 7: Program Command Sequence (LPC Mode) 1235 F06.0 LCLK LFRAME# LAD[3:0] 0000b 011Xb A[23:20] A[19:16] 0101b 0101b 0101b 1010b 0101b 1010b Tri-State TAR Load Address YYYY 5555H in 8 Clocks Write the 1st command to the device in LPC mode. Address1 1 Clock 1 Clock 1st Start Memory Write Cycle TAR Sync Data Start next Command 1 Clock 1 Clock 2 Clocks Load Data AAH in 2 Clocks 1111b 0000b LCLK LFRAME# LAD[3:0] 0000b 011Xb A[23:20] A[19:16] 1010b 1010b 1010b 0101b 0010b 0101b Tri-State TAR Load Address YYYY 2AAAH in 8 Clocks Write the 2nd command to the device in LPC mode. Address1 1 Clock 1 Clock 2nd Start Memory Write Cycle TAR Sync Data Start next Command 1 Clock 1 Clock 2 Clocks Load Data 55H in 2 Clocks 1111b 0000b LCLK LFRAME# Load Address YYYY 5555H in 8 Clocks Write the 3rd command to the device in LPC mode. 1 Clock 1 Clock 3rd Start 1 Clock 1 Clock 2 Clocks Load Data A0H in 2 Clocks LCLK LFRAME# LAD[3:0] 0000b 011Xb A[23:20] A[19:16] A[11:8] A[7:4] A[3:0] D[7:4] A[15:12] D[3:0] Tri-State TAR Load Ain in 8 Clocks Write the 4th command (target locations to be programmed) to the device in LPC mode. Address1 1 Clock 1 Clock 4th Start Memory Write Cycle TAR Sync Data Internal program start Internal program start 1 Clock 2 Clocks Load Data in 2 Clocks 1111b 0000b CE# CE# CE# CE# LAD[3:0] 0000b 011Xb A[23:20] A[19:16] 0101b 0101b 0101b 1010b 0101b 0000b Tri-State TAR Address1 TAR Sync Data Start next Command 1111b 0000b A[31:28] A[27:24] A[31:28] A[27:24] A[31:28] A[27:24] A[31:28] A[27:24] Note: 1. Address must be within memory address range specified in Table 4. |
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