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SST49LF080A 数据表(PDF) 2 Page - Microchip Technology

部件名 SST49LF080A
功能描述  8 Mbit LPC Flash
PDF  50 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

SST49LF080A 数据表(HTML) 2 Page - Microchip Technology

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©2014 Silicon Storage Technology, Inc.
DS20005086B
11/14
2
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Product Description
SST49LF080A flash memory device is designed to interface with the LPC bus for PC and Internet
Appliance application in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two
interface modes are supported: LPC mode for in-system operations and Parallel Programming (PP)
mode to interface with programming equipment.
SST49LF080A flash memory device is manufactured with proprietary, high-performance SuperFlash
Technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches. The SST49LF080A device significantly
improves performance and reliability, while lowering power consumption. The SST49LF080A device
writes (Program or Erase) with a single 3.0-3.6V power supply. It uses less energy during Erase and
Program than alternative flash memory technologies. The total energy consumed is a function of the
applied voltage, current and time of application. For any give voltage range, the SuperFlash technology
uses less current to program and has a shorter erase time; the total energy consumed during any
Erase or Program operation is less than alternative flash memory technologies. The SST49LF080A
product provides a maximum Byte-Program time of 20 µsec. The entire memory can be erased and
programmed byte-by-byte typically in 16 seconds when using status detection features such as Toggle
Bit or Data# Polling to indicate the completion of Program operation. The SuperFlash technology pro-
vides fixed Erase and Program time, independent of the number of Erase/Program cycles that have
performed. Therefore the system software or hardware does not have to be calibrated or correlated to
the cumulative number of Erase cycles as is necessary with alternative flash memory technologies,
whose Erase and Program time increase with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the SST49LF080A device is offered in 32-lead
TSOP and 32-lead PLCC packages. See Figures 2 and 3 for pin assignments and Table 1 for pin
descriptions.



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