EEPROM

AS28C010

AS28C010

Rev. 1.7 01/12

Micross Components reserves the right to change products or specifications without notice.

3

FUNCTIONAL DESCRIPTION

READ

Read operations are initiated by both OE\ and CE\

LOW. The read operation is terminated by either CE\ or OE\

returning HIGH. This two line control architecture eliminates

bus contention in a system environment. The data bus will be

in a high impedance state when either OE\ or CE\ is HIGH.

WRITE

Write operations are initiated when both CE\ and WE\ are

LOW and OE\ is HIGH. The AS28C010 supports both a CE\

and WE\ controlled write cycle. That is, the address is latched

by the falling edge of either CE\ or WE\, whichever occurs

last. Similarly, the data is latched internally by the rising edge

of either CE\ or WE\, whichever occurs first. A byte write

operation, once initiated, will automatically continue to

completion, typically within 5ms.

PAGE WRITE

The page write feature of the AS28C010 allows the entire

memory to be written in 5 seconds. Page write allows two to

two hundred fifty-six bytes of data to be consecutively written

to the AS28C010 prior to the commencement of the internal

programming cycle. The host can fetch data from another

device within the system during a page write operation (change

for each subsequent valid write cycle to the part during this

operation must be the same as the initial page address.

The page write mode can be initiated during any write operation.

Following the initial byte write cycle, the host can write an

additional one to two hundred fifty six bytes in the same manner

as the first byte was written. Each successive byte load cycle,

started by the WE\ HIGH to LOW transition, must begin within

100μs of the falling edge of the preceding WE\. If a subsequent

WE\ HIGH to LOW transition is not detected within 100μs, the

internal automatic programming cycle will commence. There

is no page write window limitation. Effectively the page write

window is infinitely wide, so long as the host continues to access

the device within the byte load cycle time of 100μs.

WRITE

The AS28C010 provides the user two write operation

status bits. These can be used to optimize a system write cycle

time. The status bits are mapped onto the I/O bus as shown in

Figure 1.

Figure 1: Status Bit Assignment

DATA\ POLLING

The AS28C010 features DATA\ Polling as a method to

indicate to the host system that the byte write or page write

cycle has completed. DATA\ Polling allows a simple bit

test operation to determine the status of the AS28C010,

eliminating additional interrupt inputs or external hardware.

During the internal programming cycle, any attempt to

read the last byte written will produce the complement of that

true data. Note: If the AS28C010 is in the protected state and

an illegal write operation is attempted DATA\ Polling will not

operate.

TOGGLE BIT

The AS28C010 also provides another method for

determining when the internal write cycle is complete. During

LOW and LOW to HIGH on subsequent attempts to read the

device. When the internal cycle is complete the toggling will

cease and the device will be accessible for additional read or

write operations.

0

4321

I/O

DP

TB

5

RESERVED

TOGGLE BIT

DATA\ POLLING