 2007-2016 Microchip Technology Inc.

DS00002256A-page 7

USB2227/USB2228

4.0

PIN DESCRIPTIONS

This section provides a detailed description of each signal. The signals are arranged in functional groups according to

their associated interface.

The “n” symbol in the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage

level. When “n” is not present before the signal name, the signal is asserted when at the high voltage level.

The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of

“active low” and “active high” signal. The term assert, or assertion indicates that a signal is active, independent of

whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive.

4.1

PIN Descriptions

Symbol

128-Pin

VTQFP

Buffer Type

Description

CompactFlash (In True IDE Mode) Interface

CF_nCS1

61

O8PU

CF Chip Select 1:

This pin is the active low chip select 1 signal for the CF ATA

device.

CF_nCS0

60

O8PU

CF Chip Select 0:

This pin is the active low chip select 0 signal for the task file

registers of CF ATA device in the True IDE mode.

CF_SA2

64

O8

CF Register Address 2:

This pin is the register select address bit 2 for the CF ATA device.

CF_SA1

63

O8

CF Register Address 1:

This pin is the register select address bit 1 for the CF ATA device.

CF_SA0

62

O8

CF Register Address 0:

This pin is the register select address bit 0 for the CF ATA device.

CF_IRQ

55

IPD

CF Interrupt:

This is the active high interrupt request signal from the CF device.

CF_D[15:8]

52

51

50

48

46

45

41

40

I/O8PD

CF Data 15-8:

The bi-directional data signals CF_D15-CF_D8 in True IDE mode

data transfer.

In the True IDE Mode, all of task file register operation occur on

the CF_D[7:0], while the data transfer is on CF_D[15:0].

The bi-directional data signal has an internal weak pull-down

resistor.

CF_D[7:0]

39

38

37

36

35

34

33

32

I/O8PD

CF Data 7-0:

The bi-directional data signals CF_D7-CF_D0 in the True IDE

mode data transfer.

In the True IDE Mode, all of task file register operation occur on

the CF_D[7:0], while the data transfer is on CF_D[15:0].

The bi-directional data signal has an internal weak pull-down

resistor.

CF_IORDY

56

IPU

IO Ready:

This pin is active high input signal.

This pin has an internally controlled weak pull-up resistor.