SAP5SD-B-G1-R datasheet(21/66 Pages) IDT

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SAP51 / SAP5S Datasheet

January 28, 2016

4.2.

User Area Programming

User Area data can be written by an ADRA or WID1 master request (see Table 3.2). Any such write access is

accompanied by two write steps to the Security_Flag, one before and one after the actual modification of user

data.

The following procedure is executed when writing to the User Area of the EEPROM:

The Security_Flag is programmed to ‘1’.

The content of the Security_Flag is read back, verifying it was programmed to ‘1’.

The user data is modified.

A read back of the written data is performed.

If the read back has proven the successful programming of the user data, the Security_Flag is

programmed back to ‘0’.

The content of the Security_Flag is read back, verifying it was programmed to ‘0’.

Successful execution of the EEPROM write procedure can be observed in the status register contents (refer to

Table 5.21). If bit S0 is set (logic HIGH), the write process is not finished yet and the programming data is still

volatile. If bit S3 (which is the Security_Flag) is set, the write procedure did not successfully complete either

because the write cycle was interrupted or due to an internal error. In order to program the data correctly, the

write request should be repeated. The status register can be read using the AS-i master call Read_Status

(RDST).

In addition to a read out of the data areas, the Security_Flag of the EEPROM is also read and evaluated during

SAP5 initialization. If the value of the Security_Flag equals ‘1’ (e.g., due to an undesired interruption of a User

Area write access), the entire User Area data is treated as corrupted (see section 5.16). The SAP5 returns to

Slave Address “0” and the ID_Code as well as the IO_Code are set to FHEX. As a result, the programming of the

User Area data can be repeated.

Table 4.2

SAP5 EEPROM – User and Firmware Area Content

Internal

EEPROM

Address

Bit Position

EEPROM Cell Contents

Description

User Area

4 to 0

A [4:0]

Slave address

2 to 0

ID1_Bit [2:0]

ID_Code_Extension_1 (user-configurable)

ID1_Bit3

ID_Code_Extension_1, A/B slave selection in Extended

Address Mode

Not implemented

3 to 0

ID1_Bit [3:0]

ID_Code_Extension_1 (manufacturer-configurable)

Not implemented

4 to 0

Not implemented

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