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SAP5SD-B-G1-R 数据表(PDF) 39 Page - Integrated Device Technology

部件名 SAP5SD-B-G1-R
功能描述  AS-Interface Spec. V3.0 Compliant Universal AS-i IC
PDF  66 Pages
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制造商  IDT [Integrated Device Technology]
网页  http://www.idt.com
标志 IDT - Integrated Device Technology

SAP5SD-B-G1-R 数据表(HTML) 39 Page - Integrated Device Technology

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SAP51 / SAP5S Datasheet
© 2016 Integrated Device Technology, Inc.
39
January 28, 2016
IO_Code
D0
D1
D2
D3
1)
P0
P1
P2
P3
1)
B
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
C
OUT
OUT
I/O
I/O
OUT
OUT
OUT
OUT
D
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
E
OUT
I/O
I/O
I/O
OUT
OUT
OUT
OUT
F
3)
PASSIV
PASSIV
PASSIV
PASSIV
OUT
OUT
OUT
OUT
1)
Slaves running in Extended_Address_Mode (ID_Code = AHEX) will output the respective select bit (I3) at the P3 pin and also at the
D3 pin if it is configured as OUT or I/O.
2)
The special case IO_Code = 7HEX causes the Parameter Ports to act as Data Inputs after DEXG master calls. Thus a bi-directional
data exchange with separate data inputs and outputs is possible. Parameter Ports are always outputs after WPAR master calls.
NOTE: IO_Code = 7HEX is not allowed for the 16-pin version of the SAP5.
3)
There is no data exchange possible if IO_Code = FHEX; i.e. Data Outputs are always at the high impedance state, and no slave
answer is generated upon reception of DEXG master calls.
Table 5.15 Data and Parameter Port Configuration in Safety Mode
Note: See section 5.18 for an explanation of F-Dx.
Package
IO_Code
D0
D1
D2
D3
P0
P1
P2
P3
1)
16 Pin
0 to 6
8 to F
F-D0*
IN
D0*
OUT
F-D2*
IN
D2*
OUT
don’t
care
don’t
care
don’t
care
don’t
care
16 Pin
7
1)
don’t
care
don’t
care
don’t
care
don’t
care
don’t
care
don’t
care
don’t
care
don’t
care
20 Pin
0 to 6
8 to F
F-D0*
IN
D0*
OUT
F-D2*
IN
D2*
OUT
P0
OUT
P1
OUT
P2
OUT
P3
OUT
20 Pin
7
2)
D0
OUT
D1
OUT
D2
OUT
D3
OUT
F-D0* IN
P0 OUT
D0* OUT
P1 OUT
F-D2* IN
P2 OUT
D2* OUT
P3 OUT
1)
IO_Code = 7HEX is not allowed for the 16-pin version for the SAP5.
2)
Parameter Ports are parameter outputs during WPAR master calls and after DEXG master calls. They are in the high impedance
state after WPAR master calls and act as inputs when a DEXG master call is performed.
5.10. Fault Indication Input PFAULT
The PFAULT fault indication input pin is provided for sensing a periphery fault-messaging signal. It contains a
high-voltage, high-impedance input stage that sets the status bit S1 of the AS-i Slave to ‘1’ if it detects a low level
at the PFAULT pin. The DC properties of the pin are specified in Table 5.5.
Signal transitions at the PFAULT pin are indicated in S1 with a slight delay because the signal is first processed
by a clock synchronizing circuit.



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